Critical IP DFT Verification Engineer
Description For Critical IP DFT Verification Engineer
Broadcom's ASIC Product Division is seeking a Senior DFT Verification Engineer for their Shanghai Design Center. This role focuses on ensuring the robustness and reliability of HBM, DDR, and SerDes designs through comprehensive Design for Test (DFT) verification strategies. The position offers an opportunity to work with cutting-edge semiconductor technology and collaborate with global teams.
The ideal candidate will lead DFT verification efforts, working closely with cross-functional teams to develop and implement testing methodologies. They will be responsible for crucial aspects of the semiconductor development process, from initial design verification to silicon bring-up and customer support. The role requires expertise in both analog and digital domains, with a strong foundation in DFT methodologies.
This position offers the chance to work on advanced semiconductor technologies at 3nm and beyond, contributing to innovative solutions for complex testability challenges. The role combines technical leadership with hands-on engineering work, requiring both deep technical expertise and strong collaborative skills.
Broadcom provides a dynamic work environment where engineers can contribute to cutting-edge semiconductor solutions while working with global teams. The company's position as a global technology leader offers excellent opportunities for professional growth and impact in the semiconductor industry.
Responsibilities For Critical IP DFT Verification Engineer
- Implement and verify DFT methodologies for HBM, DDR and SerDes designs
- Collaborate with design and architecture teams to identify testability requirements
- Utilize simulation tools to verify DFT implementations
- Analyze DFT-related data and provide insights for improvements
- Document verification processes and results
- Generate, verify and debug test vectors
- Validate test vectors on ATE during silicon bring up
- Assist with silicon failure analysis and yield improvement
- Interface with customers and global teams
- Automate DFT and Test Vector Generation flows
Requirements For Critical IP DFT Verification Engineer
- Strong DFT background (Analog DFT, MBIST, IEEE1687)
- Experience in DFT verification with HBM, DDR, PCIE and SerDes IPs
- Understanding of DFT methodologies including scan, BIST, and ATPG
- Proficiency in simulation tools and scripting (Perl, Python, TCL, Ruby)
- Knowledge in analog and digital circuit design
- Bachelor's in Electrical/Electronic/Computer Engineering with 8+ years experience or Master's with 6+ years experience
- Excellent problem solving and communication skills
- Experience with ATE (preferred)
- Knowledge of AHB/APB/AXI buses (preferred)
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