Lead CPU RTL Front End Design Engineer, Subsystem
Description For Lead CPU RTL Front End Design Engineer, Subsystem
Google is seeking a Lead CPU RTL Front End Design Engineer to join their hardware team, focusing on developing custom silicon solutions that power Google's direct-to-consumer products. This role requires extensive experience in digital logic design and RTL concepts, with a focus on CPU subsystem development. The position offers an opportunity to work on next-generation CPU architectures, combining technical leadership with hands-on design work.
The ideal candidate will have at least 10 years of experience in RTL design and digital logic, with a strong background in computer architecture. They will lead front-end design efforts for CPU components, working closely with verification, physical design, and power teams to deliver high-quality solutions that meet performance, power, and area goals.
This role offers competitive compensation including a base salary range of $221,000-$314,000, plus bonus, equity, and comprehensive benefits. The position is available in several prestigious locations including Mountain View, CA and Austin, TX, allowing flexibility for qualified candidates.
Working at Google means being part of a diverse team that pushes boundaries and develops innovative hardware solutions. The role involves collaboration with various teams, including Software, Architecture, and Performance, to drive the next generation of hardware experiences that will impact millions of users worldwide.
The position requires strong technical expertise combined with leadership skills, as you'll be responsible for proposing and implementing performance-enhancing microarchitecture features, conducting trade-off studies, and ensuring the delivery of production-quality designs. This is an excellent opportunity for someone looking to make a significant impact in hardware design at one of the world's leading technology companies.
Responsibilities For Lead CPU RTL Front End Design Engineer, Subsystem
- Participate in developing CPU subsystem. Develop CPU subsystem front-end designs, emphasizing on microarchitecture and RTL design for the next generation CPU
- Communicate the pros and cons of microarchitecture enhancements. Deliver designs, meeting PPA goals with production quality
- Work with the Verification team to ensure production of quality designs, and the physical design and power teams to meet frequency, power, and area goals
- Become familiar with modern techniques, interpret the techniques into design constructs and languages to provide guidance to and participate in the performance evaluation effort
- Propose performance enhancing microarchitecture features, and work with Software, Architect, and Performance teams for trade-off studies
Requirements For Lead CPU RTL Front End Design Engineer, Subsystem
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience
- 10 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog
- Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques
- Experience with RTL language (System Verilog) and related design processes (e.g., Lint, UPF)
Benefits For Lead CPU RTL Front End Design Engineer, Subsystem
- bonus
- equity
- benefits
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