SoC Performance Verification Engineer, Silicon
Description For SoC Performance Verification Engineer, Silicon
Google is seeking a SoC Performance Verification Engineer to join their hardware team working on custom silicon solutions for direct-to-consumer products. This role is crucial in developing and verifying the next generation of Google's Tensor SOC, which powers their innovative hardware experiences. The position requires strong expertise in design verification, particularly with SystemVerilog/UVM and formal verification techniques. You'll work with cutting-edge technology, collaborating with system architects and various hardware teams to ensure optimal performance of Google's silicon solutions. The role offers the opportunity to impact millions of users worldwide while working with state-of-the-art hardware and AI technologies. You'll be responsible for developing simulators, conducting architectural evaluations, and performing critical pre-silicon performance simulations. The ideal candidate should have a strong background in electrical engineering or computer science, with significant experience in digital logic verification and working with complex microprocessor systems. This position offers the chance to be part of Google's mission to create radically helpful experiences through the perfect blend of AI, software, and hardware technologies.
Responsibilities For SoC Performance Verification Engineer, Silicon
- Develop simulators and architectural models of Google's Tensor SOC
- Participate in architectural and design evaluation of Tensor SOC features studies
- Collaborate with system architects, SoC and CPU/GPU/TPU architects/designers, and software and application experts
- Perform pre-silicon performance simulation and correlate with pre and post-silicon measurements
- Communicate analysis results qualitatively and quantitatively
Requirements For SoC Performance Verification Engineer, Silicon
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
- 4 years of experience with Design Verification with 2 years in formal verification
- Experience in verifying digital logic at RTL level using Systemverilog/UVM and FV Techniques
- Experience with digital systems using standard IP components/interconnects (microprocessor cores, hierarchical memory subsystems)
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