ASIC Engineer, Design Verification

Meta is hiring an ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications.

As a Design Verification Engineer, you will be part of a dynamic team working with the best in the industry, focused on developing innovative ASIC solutions for Facebook's data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure. Along with traditional simulation, you will be able to use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.

Responsibilities:

• Define and implement block/IP/SoC verification plans, build verification test benches to enable block/IP/sub-system/SoC level verification
• Develop functional tests based on verification test plan
• Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
• Debug, root-cause and resolve functional failures in the design, partnering with the Design team
• Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality

Minimum Qualifications:

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• 5+ years hands-on experience in SystemVerilog/UVM methodology or C/C++ based verification
• Track record of 'first-pass success' in ASIC development cycles
• 5+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
• Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
• Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle

Preferred Qualifications:

• Experience in development of UVM based verification environments from scratch
• Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs
• Experience with revision control systems like Mercurial(Hg), Git or SVN
• Experience with verification of ARM/RISC-V based sub-systems or SoCs
• Experience with IP or integration verification of high-speed interfaces like PCIe, DDR, Ethernet

Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology.