Design-for-Testability Engineer
Description For Design-for-Testability Engineer
Amazon Lab126, the innovative team behind the Silicon IP AZ1 Neural Edge powering Echo devices, is seeking a Senior DFT Engineer to drive innovation in hardware development. This role is part of the team that revolutionized reading with Kindle and transformed user experience through Echo and Alexa.
As a Design-for-Testability (DFT) Engineer, you'll be involved in the complete device lifecycle, from initial architecture definition to high-volume production. The position demands expertise in multiple aspects of chip design, including architecture definition, logic design, verification, and test pattern generation.
Working closely with various VLSI engineering teams, you'll contribute to DFT logic design, manage test pattern sign-offs, perform timing analysis, and handle silicon testing and validation. This role offers an opportunity to impact Amazon's next-generation ML accelerator development at the edge.
The ideal candidate brings 5+ years of semiconductor experience, strong technical skills in chip design and verification, and expertise in DFT methodologies. You should be proficient in Verilog, System Verilog, and various testing tools and methodologies. The role requires excellent communication skills, attention to detail, and the ability to work effectively in a fast-paced environment.
Join us in shaping the future of Amazon's device ecosystem, working with cutting-edge technology in ML acceleration and edge computing. This position offers the chance to be part of a team that consistently pushes boundaries in consumer technology, making history while maintaining Amazon's commitment to innovation and customer-centric solutions.
Responsibilities For Design-for-Testability Engineer
- Contribute to the design and verification of DFT logic and components
- Drive the sign-off on high-quality test and debug patterns for high coverage on silicon
- Review sign-off level timing closure using static timing analysis of DFT modes
- Perform wafer probe testing, ATE testing, silicon bring-up, diagnosis and support for physical failure analysis
- Take high volume chips to production with high coverage ATE test program
Requirements For Design-for-Testability Engineer
- BS degree in Computer Engineering/Electrical Engineering
- 5+ years in semiconductor companies as a DFT lead/manager
- Chip design experience in Verilog and System Verilog
- Chip verification experience, UVM methodology
- Experience with scan insertion tools and methodologies
- MBIST and BISR, BIHR insertion tools and methodologies
- EFUSE controllers and related structures
- Top level DFT architecture definition experience
- Gate-level simulations
- Static timing analysis, DFT related timing closure
- Scripting (Perl/Tcl)
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