Sr. Static Timing Technical Lead, Hardware Compute Group

A technology company that revolutionized reading with Kindle and reimagined user experience through Echo and Alexa.
Portland, OR, USA
Embedded
Principal Software Engineer
In-Person
10+ years of experience
AI · Consumer

Description For Sr. Static Timing Technical Lead, Hardware Compute Group

Amazon Lab126, the innovative team behind the Silicon IP AZ1 Neural Edge powering Echo devices, is seeking a Senior Static Timing Technical Lead for their Hardware Compute Group. This role is crucial for developing and implementing timing signoff methodologies for complex SoC designs. The position combines technical leadership in static timing analysis with hands-on implementation of advanced signoff flows.

The role offers an opportunity to work on cutting-edge ML accelerator technology at the edge, contributing to products that impact millions of users. You'll be part of the team that revolutionized reading with Kindle and transformed user experience through Echo and Alexa. The position requires expertise in SoC timing constraints, multi-clock/multi-voltage systems, and advanced timing signoff flows.

As a technical lead, you'll collaborate across multiple teams, including Systems Architecture, SoC Integration, Verification, and Mixed Signal, addressing complex design challenges. The role demands both technical depth in timing analysis and breadth in understanding various aspects of chip design.

The ideal candidate brings extensive semiconductor implementation experience, strong scripting abilities, and proficiency with industry-standard tools. You'll need excellent communication skills to work effectively with distributed teams and drive innovation in timing methodology.

This position at Amazon offers the chance to work on next-generation hardware products while being part of a culture that emphasizes innovation and customer focus. The company's commitment to diversity and inclusion ensures a supportive environment for professional growth and impact.

Last updated 11 minutes ago

Responsibilities For Sr. Static Timing Technical Lead, Hardware Compute Group

  • Define and develop signoff methodology and implementation solutions
  • Develop full chip timing constraints and perform STA signoff for complex multi-clock, multi-voltage SoC
  • Streamline timing signoff criterions and analysis methodologies
  • Implement advance timing signoff flows (AOCV, POCV Based STA, IR Drop aware STA)
  • Collaborate with various teams to address design challenges
  • Perform multi-corner and multimode analysis
  • Close timing at signoff corners covering all modes and delay corners

Requirements For Sr. Static Timing Technical Lead, Hardware Compute Group

Python
Linux
  • Bachelor's degree or higher in EE, CE, or CS
  • 10+ years of practical semiconductor implementation experience
  • Scripting experience with Perl, Python, tcl, shell
  • Proficiency in chip front-end and back-end implementation tools
  • Good communication and analytical skills
  • Ability to work with IP Design teams and Backend Physical Design teams across multiple sites

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