ASIC Design Engineer - Pixel IP
Description For ASIC Design Engineer - Pixel IP
Apple's Hardware Technologies group is seeking an ASIC Design Engineer to join their Pixel IP design team. This role is crucial in developing next-generation, high-performance, power-efficient system-on-chips (SoCs) that power Apple's renowned devices. As part of this highly transparent position, you'll be at the heart of creating pixel processing engines that deliver breathtaking images and video to millions of customers worldwide.
The role involves close collaboration with multiple teams, including chip integration, physical design, power, logic design, and verification. You'll be responsible for integrating large pixel-processing subsystems using SystemVerilog, managing clock domains, and implementing sophisticated front-end designs. Your expertise will be essential in delivering high-performance, low-power solutions that maintain Apple's reputation for excellence.
Working at Apple means joining a company that values innovation and technical excellence. You'll receive competitive compensation, including base pay ranging from $143,100 to $264,200, plus opportunities for stock awards and bonuses. The comprehensive benefits package includes medical and dental coverage, retirement benefits, and education reimbursement.
The ideal candidate brings at least 3 years of industry experience, strong knowledge of ASIC/FPGA design methodologies, and expertise in front-end implementation. You'll need excellent communication skills and the ability to work effectively in a collaborative environment. This is an opportunity to make a significant impact on products used by millions while working with cutting-edge technology in a supportive and dynamic environment.
Responsibilities For ASIC Design Engineer - Pixel IP
- Integration of large pixel-processing subsystems using SystemVerilog
- Writing detailed micro-architectural specifications
- Performing front-end implementation including logic synthesis
- Working with Physical Design teams for physical floorplanning
- Collaborating with teams to improve performance while minimizing power and area
- Working with design verification and formal verification teams
Requirements For ASIC Design Engineer - Pixel IP
- BS and a minimum of 3 years relevant industry experience
- Experience in IP/SoC front-end ASIC RTL digital logic design using Verilog and System Verilog
- Experience in ASIC implementation, logic synthesis, static timing analysis
- Experience with system design methodologies with multiple clock domains
- Knowledge of low-power design issues, tools, and methodologies including UPF
- Familiarity with common on-chip bus protocols such as AMBA
- Knowledge of ASIC/FPGA design methodology
- Excellent written and verbal communication skills
Benefits For ASIC Design Engineer - Pixel IP
- Comprehensive medical and dental coverage
- Retirement benefits
- Employee stock programs
- Education reimbursement
- Discretionary bonuses
- Relocation assistance
- Employee discount on products
- Free services
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