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Cellular SOC Design Verification Engineer

A leading technology company that designs and develops consumer electronics, software, and services.
$80,000 - $120,000
Embedded
Entry-Level Software Engineer
In-Person
5,000+ Employees
Hardware
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Description For Cellular SOC Design Verification Engineer

Join Apple's Silicon Engineering Group as a Design Verification Engineer working on cutting-edge Cellular SoCs. This role offers an opportunity to be at the heart of verification efforts within the silicon design group, responsible for creating and productizing state-of-the-art Cellular SoCs. You'll work on integrating sophisticated IP level DV environments, creating UVM-based test benches, and implementing coverage-driven test suites. The position provides extensive learning opportunities in large-scale SOC design, complex verification test benches, SOC architectures, high-speed protocols, and industry-standard low power architecture. You'll gain knowledge in Cellular protocol, FW-HW interactions, and multi-chip SOC debug architecture. Working with Apple's product development teams, you'll push the boundaries of cellular systems and enhance product experiences for customers worldwide. The ideal candidate should possess strong programming skills, particularly in SystemVerilog, Python, and C++, with a solid foundation in digital design and computer architecture. This role combines technical expertise with collaborative teamwork, offering a chance to contribute to groundbreaking cellular technology developments at Apple.

Last updated 6 months ago

Responsibilities For Cellular SOC Design Verification Engineer

  • Contribute to verification effort of complex SOCs delivering Cellular solution
  • Integrate multiple sophisticated IP level DV environments
  • Craft highly reusable UVM based test bench
  • Implement effective coverage driven and directed test suites
  • Deploy new tools and methodologies
  • Collaborate with other product development groups

Requirements For Cellular SOC Design Verification Engineer

Python
  • BSEE or BSCS is required
  • Object Oriented Programming
  • Coursework in Digital Design
  • Programming experience in SystemVerilog, Python, C++
  • Coursework in Computer Architecture, Networking Protocol

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