DDR Design Engineer
Description For DDR Design Engineer
Apple is seeking a DDR Design Engineer to join their Hardware team in San Diego. This role offers a unique opportunity to work on cutting-edge products that impact millions of customers. As part of the DDR PHY design team, you'll be responsible for creating best-in-class PHY designs for high-performance, low power applications. The position involves all phases of design, from concept to silicon implementation.
The ideal candidate will have strong expertise in RTL design, digital logic, and hardware verification. You'll be working with state-of-the-art tools and technologies to ensure the highest quality in chip design. The role requires collaboration with cross-functional teams including architecture, circuit design, and verification engineers.
Apple offers a competitive compensation package, including base pay ranging from $135,400 to $250,600, plus additional benefits like stock options, comprehensive healthcare, and educational reimbursement. This is an excellent opportunity for an experienced engineer to contribute to groundbreaking technology development at one of the world's most innovative companies.
The position requires a minimum of 3 years of experience and a BS in a technical discipline. Key technical skills include Verilog/SystemVerilog, state machine design, and understanding of digital design principles. Experience with DDR PHY design and mixed-signal environment is advantageous. Join Apple's dynamic team and be part of creating the next generation of revolutionary products.
Responsibilities For DDR Design Engineer
- Perform concept studies and provide direction for performance, gate count and power for various digital designs
- Write detailed design specification and test plans with architecture, circuit designers and verification engineers
- Provide high-quality RTL description, including assertions, for the design
- Use formal tools and static checkers to guarantee RTL quality
- Support design verification to ensure bug-free first silicon
- Drive functional and code coverage and timing closure for designs
- Support silicon bring-up, performance and power characterization
Requirements For DDR Design Engineer
- BS degree in technical discipline with minimum 3 years of relevant experience
- RTL design using Verilog or SystemVerilog, assertion writing
- Design of state machines, data paths, arbitration and clock domain crossing logic
- Logic synthesis, timing constraints
- Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL
- Unified Power Format for simulation, synthesis and electrical rule checking Equivalence checking
Benefits For DDR Design Engineer
- Comprehensive medical and dental coverage
- Retirement benefits
- Employee stock programs
- Discounted products and free services
- Education reimbursement
- Discretionary bonuses
- Relocation assistance
- Employee Stock Purchase Plan
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