Design Verification Engineer
Description For Design Verification Engineer
Join an accomplished team at Apple developing custom integrated circuits for Apple's existing and future product lines. As a member of our mixed signal ASIC team, you will be responsible for verifying complex digital IP's. You will work with system architects and digital designers, making block level specifications clear and precise. You will use the specifications to build verification plans to exercise the functional, performance, stress cases, and error conditions in your blocks. You will own the creation of verification testbenches, using formal verification and UVM based simulation. Then you will build testcases using System Verilog Assertions and constrained random UVM testcases to get complete functional and code coverage for your blocks.
You will participate in code reviews of other blocks in the chips, offering proposals to more efficiently achieve our goal of bug-free designs on the first tapeout. In addition to traditional digital circuit simulation, you will have the opportunity to learn and use other verification techniques such as formal verification, digital mixed signal verification, and analog mixed signal simulation using state-of-the-art tools.
Although the team is small, we supply silicon to most of Apple's industry-leading hardware development teams. We have a close-knit, high-performing team ready to mentor engineers entering the mixed signal ASIC development field. Join us in building Apple's next generation products. Do you want to be a part of building the "surprise and delight" in Apple's future products?
This role offers a competitive base pay range of $58.61 to $88.29 per hour, along with additional benefits such as:
- Comprehensive medical and dental coverage
- Retirement benefits
- Employee stock programs (discretionary restricted stock unit awards and employee stock purchase plan)
- Discounted products and free services
- Reimbursement for certain educational expenses related to advancing your career at Apple
- Potential eligibility for discretionary bonuses or commission payments
- Relocation benefits may be available
Apple is committed to inclusion, diversity, and equal opportunity employment. We consider all qualified applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
Responsibilities For Design Verification Engineer
- Collaborate in developing precise design specifications for digital control blocks
- Use design specifications to create block and chip level verification plans
- Architect and create block level verification elements
- Assist in architecting chip and system level verification environments
- Use System Verilog and UVM to develop drivers, tests, reference models and checkers
- Debug test failures and work with designers to develop fixes
- Use functional and code coverage to track progress and gauge tapeout readiness
Requirements For Design Verification Engineer
- Masters' degree or higher in Electrical Engineering or Computer Science
- Extensive course work in digital design and computer architecture
- Foundation in object oriented programming techniques
- Lab courses or work experience with System Verilog
- Familiar with constrained random verification techniques
- Familiarity with clock domain crossing design and verification techniques
- Some course work in analog circuit design
Benefits For Design Verification Engineer
- Medical Insurance
- Dental Insurance
- Vision Insurance
- 401k
- Equity
- Education Budget
