Design Verification Engineer
Description For Design Verification Engineer
Apple is seeking a Design Verification Engineer to join their hardware team in crafting innovative products that impact millions of customers. This digital-focused DV engineering role involves ensuring bug-free first silicon for SoC/IP designs. The position requires expertise in pre-silicon verification, including methodology establishment, test-plan development, and verification environment creation. You'll work on developing scalable test-benches, managing coverage analysis, and ensuring successful tape-outs. The role offers comprehensive benefits, competitive compensation ($143,100-$264,200), and the opportunity to work on cutting-edge hardware projects. Apple provides a collaborative environment with opportunities for growth, stock programs, and various professional development benefits. The ideal candidate will have strong skills in SystemVerilog, UVM, and verification methodologies, with experience in protocol implementations and automation tools.
Responsibilities For Design Verification Engineer
- Establish DV methodology
- Develop test-plan
- Create verification environment including stimulus and checkers
- Test-writing and debugging
- Coverage analysis
- Sign-off for RTL freeze and tape-out
- Develop verification plans for all features
- Execute verification plans
- Develop block, IP and SoC level test-benches
- Track and report DV progress
Requirements For Design Verification Engineer
- BS degree in technical discipline with minimum 3 years of relevant experience
- Deep knowledge of SystemVerilog and UVM
- Deep knowledge in developing scalable and portable test-benches
- Experience with verification methodologies and tools
- Knowledge of build and run automation, coverage collection, gate level simulations
- C/C++ knowledge
- Experience with serial protocols (PCIe or USB) and parallel protocol (DDR)
- Basic knowledge of formal verification methodology
- Experience with power-aware (UPF) verification methodology
- Knowledge of scripting languages (Python, Perl, TCL)
Benefits For Design Verification Engineer
- Comprehensive medical and dental coverage
- Retirement benefits
- Employee stock programs
- Discounted products and free services
- Education reimbursement
- Discretionary bonuses
- Commission payments
- Relocation benefits
Jobs Related To Apple Design Verification Engineer
