Design Verification Engineer

A technology company that crafts products that enrich people's lives
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Mid-Level Software Engineer
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3+ years of experience
Hardware

Description For Design Verification Engineer

At Apple, we work every single day to craft products that enrich people's lives. As a Design Verification Engineer, you'll join a dynamic group working on challenges that no one has solved yet. This role focuses on producing fully functional first silicon for Analog/Digital IP designs.

You'll be responsible for all phases of pre-silicon verification, including establishing DV methodology, test-plan development, verification environment development, and ensuring bug-free first silicon for part of the SoC / IP. The role requires expertise in SystemVerilog, UVM, and verification methodologies.

Working at Apple means being part of a team that crafts upcoming products that will impact millions of customers. You'll develop verification environments, execute test plans, and work closely with the analog team to ensure overall bug-free IP design. Your work will directly contribute to the quality and reliability of Apple's innovative hardware products.

The ideal candidate will have strong technical skills in verification methodologies, experience with IP developments, and excellent knowledge of scripting languages. You'll be working with cutting-edge technology and have the opportunity to solve complex challenges in hardware verification.

Join Apple's hardware team and be part of creating the next generation of revolutionary products that delight and inspire users worldwide. This role offers the rare opportunity to work on projects that push the boundaries of technology while maintaining Apple's high standards for quality and innovation.

Last updated 4 hours ago

Responsibilities For Design Verification Engineer

  • Develop detailed test and coverage plans based on the micro-architecture
  • Develop verification methodology suitable for the IP
  • Develop verification environment, including stimulus, checkers, assertions, trackers, coverage
  • Execute verification plans, including design bring-up, DV environment bring-up
  • Develop block, IP and SoC level test-benches
  • Track and report DV progress using various metrics
  • Develop IP simulation environment
  • Work closely with analog team to ensure overall bug-free IP design

Requirements For Design Verification Engineer

Python
  • BS degree in technical discipline with minimum 3 years of relevant experience
  • Advanced knowledge of SystemVerilog and UVM
  • Experience developing scalable and portable test-benches
  • Experience with verification methodologies and tools
  • Experience with serial protocols such as PCIe or USB
  • Experience with IP verification method
  • Deep knowledge with IPs developments such as PHYs, PLLs etc.
  • Excellent knowledge of one of the scripting languages: Python, Perl, TCL
  • Proven knowledge of formal verification methodology

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