Design Verification Engineer

A technology company that crafts products that enrich people's lives
Embedded
Staff Software Engineer
In-Person
10+ years of experience
Hardware

Description For Design Verification Engineer

At Apple, we work every single day to craft products that enrich people's lives. As a Design Verification Engineer, you'll join a dynamic group working on challenges that no one has solved yet. This role focuses on producing fully functional first silicon for Analog/Digital IP designs.

You'll be responsible for all phases of pre-silicon verification, including establishing DV methodology, test-plan development, verification environment development, and ensuring bug-free first silicon for part of the SoC / IP. The position requires expertise in SystemVerilog, UVM, and verification methodologies, working with cutting-edge hardware designs.

The role offers the rare opportunity to impact millions of Apple's customers through your work on upcoming products. You'll collaborate with the analog team, develop sophisticated verification environments, and ensure the quality of complex hardware designs. Your work will directly contribute to Apple's next-generation products, making this an exciting opportunity for someone passionate about hardware verification and quality assurance.

Working at Apple means joining a company committed to innovation and excellence. You'll be part of a team that values technical expertise, creative problem-solving, and attention to detail. The position offers the chance to work on challenging projects that push the boundaries of technology while maintaining Apple's high standards for quality and reliability.

Last updated 16 days ago

Responsibilities For Design Verification Engineer

  • Develop detailed test and coverage plans based on the micro-architecture
  • Develop verification methodology suitable for the IP
  • Develop verification environment including stimulus, checkers, assertions, trackers, coverage
  • Execute verification plans including design bring-up, DV environment bring-up
  • Track and report DV progress using various metrics
  • Develop IP simulation environment
  • Work closely with analog team to ensure overall bug-free IP design

Requirements For Design Verification Engineer

Python
  • BS degree in technical subject area with minimum 10 years of proven experience
  • Advanced knowledge of SystemVerilog and UVM
  • Experience developing scalable and portable test-benches
  • Experience with verification methodologies and tools
  • Experience with serial protocols such as PCIe or USB
  • Experience with IP verification method
  • Deep knowledge with IPs developments such as PHYs, PLLs etc.
  • Excellent knowledge of one of the scripting languages: Python, Perl, TCL
  • Proven knowledge of formal verification methodology

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