Design Verification Engineer

A technology company that crafts products that enrich people's lives, known for innovative hardware and software solutions.
$143,100 - $264,200
Embedded
Mid-Level Software Engineer
In-Person
5,000+ Employees
3+ years of experience
Hardware

Description For Design Verification Engineer

Apple is seeking a Design Verification Engineer to join their hardware team in crafting innovative products that impact millions of customers. This digital-focused DV engineering role involves ensuring bug-free first silicon for SoC/IP designs. The position requires expertise in pre-silicon verification, including methodology establishment, test-plan development, and verification environment creation. The ideal candidate will work on developing scalable verification environments, execute comprehensive verification plans, and handle debug processes. This role offers the unique opportunity to work on cutting-edge hardware projects at one of the world's leading technology companies, with competitive compensation including base pay, stock options, and comprehensive benefits. The position combines technical challenges with the opportunity to impact Apple's next-generation products, making it ideal for engineers passionate about hardware verification and quality assurance. The role offers growth potential, exposure to advanced technologies, and the chance to work with industry-leading professionals in hardware development.

Last updated 25 minutes ago

Responsibilities For Design Verification Engineer

  • Establish DV methodology and test-plan development
  • Develop verification environment including stimulus and checkers
  • Test-writing, debug, and coverage analysis
  • Sign-off for RTL freeze and tape-out
  • Develop detailed test and coverage plans based on micro-architecture
  • Ensure bug-free first silicon for part of the SoC / IP
  • Track and report DV progress using various metrics
  • Develop block, IP and SoC level test-benches

Requirements For Design Verification Engineer

Python
Linux
  • BS degree in technical discipline with minimum 3 years of relevant experience
  • Deep knowledge of SystemVerilog and UVM
  • Deep knowledge in developing scalable and portable test-benches
  • Experience with verification methodologies and tools
  • Knowledge of C/C++
  • Experience with serial protocols (PCIe, USB) and parallel protocols (DDR)
  • Basic knowledge of formal verification methodology
  • Knowledge of scripting languages (Python, Perl, TCL)

Benefits For Design Verification Engineer

Medical Insurance
Dental Insurance
401k
Equity
Education Budget
Relocation Benefits
  • Comprehensive medical and dental coverage
  • Retirement benefits
  • Employee stock programs
  • Discounted products and free services
  • Education reimbursement
  • Discretionary bonuses
  • Relocation assistance
  • Employee Stock Purchase Plan

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