Design Verification Engineer
Description For Design Verification Engineer
At Apple, we're seeking an exceptional Design Verification Engineer to join our Hardware team in crafting products that impact millions of customers worldwide. This role focuses on digital DV engineering, enabling the production of fully functional first silicon for IP designs. The position offers a unique opportunity to work on cutting-edge technology in a company known for innovation.
As a Design Verification Engineer, you'll be instrumental in ensuring bug-free first silicon for SoC/IP components. Your responsibilities will span all phases of pre-silicon verification, from establishing methodologies to final tape-out. You'll work with advanced technologies including SystemVerilog, UVM, and various verification tools.
The ideal candidate brings deep expertise in verification methodologies, test-bench development, and protocol knowledge. You'll be responsible for developing scalable verification environments, creating comprehensive test plans, and ensuring quality through rigorous testing and debugging processes. This role offers the opportunity to work on challenging problems that haven't been solved before, contributing to products that delight millions of Apple customers.
Working at Apple means joining a team that values innovation, quality, and attention to detail. You'll collaborate with talented engineers while having access to cutting-edge tools and technologies. The position offers the rare opportunity to influence the development of future Apple products while working in an environment that encourages creativity and technical excellence.
If you're passionate about verification engineering, have a strong technical background, and want to be part of creating products that shape the future of technology, this role offers an exceptional opportunity to make a significant impact at one of the world's most innovative companies.
Responsibilities For Design Verification Engineer
- Establish DV methodology and test-plan development
- Develop verification environment including stimulus and checkers
- Test-writing, debug, coverage, sign-off for RTL freeze and tape-out
- Ensure bug-free first silicon for part of the SoC / IP
- Develop detailed test and coverage plans based on micro-architecture
- Develop verification methodology suitable for the IP
- Track and report DV progress using metrics including bugs and coverage
- Debug test failures
Requirements For Design Verification Engineer
- BS degree in technical subject area with minimum 10 years of proven experience
- Deep knowledge of SystemVerilog and UVM
- Deep knowledge in developing scalable and portable test-benches
- Experience with verification methodologies and tools
- Deep UVM knowledge, C/C++ level knowledge
- Deep experience with serial protocols such as PCIe or USB, parallel protocol such as DDR
- Experience with power-aware (UPF) or similar verification methodology
- Excellent knowledge of scripting languages such as Python, Perl, TCL
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