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Design Verification Engineer

A technology company that crafts products that enrich people's lives
$135,400 - $250,600
Embedded
Mid-Level Software Engineer
In-Person
5,000+ Employees
3+ years of experience
Hardware
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Description For Design Verification Engineer

Apple is seeking a Design Verification Engineer to join their hardware team in crafting innovative products that impact millions of customers. This role focuses on ensuring bug-free first silicon for IP designs, requiring expertise in pre-silicon verification, test-plan development, and verification environment creation. The position offers a comprehensive benefits package including medical coverage, stock options, and educational support. The ideal candidate will have strong experience in SystemVerilog, UVM, and verification methodologies, working on complex hardware verification challenges. This is an opportunity to work with cutting-edge technology at one of the world's leading tech companies, with competitive compensation ranging from $135,400 to $250,600. The role combines technical expertise with collaborative teamwork, particularly with analog teams, to ensure overall design quality. Apple's commitment to inclusion and diversity, along with their extensive benefits package, makes this an attractive opportunity for experienced verification engineers looking to make an impact in hardware development.

Last updated 4 months ago

Responsibilities For Design Verification Engineer

  • Develop detailed test and coverage plans based on micro-architecture
  • Develop verification methodology suitable for the IP
  • Develop verification environment including stimulus, checkers, assertions, trackers, coverage
  • Develop verification plans for all features
  • Execute verification plans including design bring-up
  • Develop block, IP and SoC level test-benches
  • Track and report Design Verification progress
  • Work closely with analog team to ensure overall bug-free IP design

Requirements For Design Verification Engineer

Python
  • BS degree in technical subject area
  • Minimum 3 years of meaningful experience
  • Solid understanding of SystemVerilog test-bench language and UVM
  • Experience developing scalable and portable test-benches
  • Experience with verification methodologies and tools
  • Experience with serial protocols such as PCIe or USB
  • Working knowledge with scripting languages: Python, Perl, TCL
  • Proven experience in formal verification methodology

Benefits For Design Verification Engineer

Medical Insurance
Dental Insurance
Education Budget
Equity
Relocation Benefits
  • Comprehensive medical and dental coverage
  • Retirement benefits
  • Discounted products and free services
  • Education reimbursement
  • Employee stock programs
  • Discretionary restricted stock unit awards
  • Employee Stock Purchase Plan
  • Discretionary bonuses
  • Relocation benefits

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