Design Verification Engineer
Description For Design Verification Engineer
Apple, a leading consumer technology company, is seeking a Design Verification Engineer to join their Hardware team in San Diego. This role offers an exciting opportunity to work on cutting-edge products that impact millions of users worldwide. As a Design Verification Engineer, you'll be responsible for ensuring bug-free first silicon for IP designs, working with state-of-the-art verification methodologies and tools.
The position requires expertise in developing verification environments, test plans, and coverage strategies. You'll work with SystemVerilog, UVM, and various verification tools while collaborating closely with cross-functional teams. The role offers exposure to complex SoC designs and IP verification, making it perfect for engineers passionate about hardware verification.
Apple offers a competitive compensation package ranging from $135,400 to $250,600, along with comprehensive benefits including medical coverage, stock options, and education reimbursement. This is an excellent opportunity for experienced verification engineers looking to make an impact at one of the world's most innovative technology companies.
The ideal candidate will have at least 3 years of experience, strong technical skills in verification methodologies, and a passion for quality and attention to detail. You'll be part of a team that values innovation, collaboration, and technical excellence, working on products that define the future of technology.
Responsibilities For Design Verification Engineer
- Develop detailed test and coverage plans based on micro-architecture
- Develop verification methodology suitable for the IP
- Develop verification environment including stimulus, checkers, assertions, trackers, coverage
- Execute verification plans including design bring-up
- Develop block, IP and SoC level test-benches
- Track and report Design Verification progress
- Work closely with analog team to ensure overall bug-free IP design
Requirements For Design Verification Engineer
- BS degree in technical subject area
- Minimum 3 years of meaningful experience
- Solid understanding of SystemVerilog test-bench language and UVM
- Experience with verification methodologies and tools
- Working knowledge with scripting languages: Python, Perl, TCL
- Experience with serial protocols such as PCIe or USB
Benefits For Design Verification Engineer
- Comprehensive medical and dental coverage
- Retirement benefits
- Employee stock programs
- Education reimbursement
- Discretionary restricted stock unit awards
- Employee Stock Purchase Plan with discount
- Discretionary bonuses
- Relocation benefits
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