Design Verification Engineer
Description For Design Verification Engineer
Apple is seeking a Design Verification Engineer to join their dynamic hardware team in creating groundbreaking products. As a crucial member of the chip design effort, you'll collaborate across all disciplines in a vertical product model, working on challenges that directly impact millions of customers. The role involves ensuring SOC quality, developing test methodologies, and working closely with design and micro-architecture teams.
The position offers a competitive base salary range of $121,900 to $183,600, along with comprehensive benefits including medical coverage, retirement plans, and various stock programs. You'll be part of Apple's innovative culture where new ideas quickly transform into extraordinary products.
The ideal candidate should have a strong background in CPU & SOC architecture, proficiency in low-level programming, and expertise in verification methodologies. You'll need excellent problem-solving skills and the ability to work both independently and collaboratively.
This is an exceptional opportunity to be at the forefront of hardware innovation, working with cutting-edge technology and contributing to products that define industry standards. You'll be part of a team that values creativity, technical excellence, and commitment to quality, while enjoying the benefits of working for one of the world's most influential technology companies.
Responsibilities For Design Verification Engineer
- Ensuring the quality of the SOC
- Working closely with the team to review specifications, develop attributes, tests & coverage plans, and define methodology & test benches
- Teaming up with the design and micro-architecture teams to understand the functional and performance goals of the design
- Work independently and manage deliverables to align with the project goals plus support cross-functional engineering efforts
Requirements For Design Verification Engineer
- BSEE/CS or MSEE/CS
- Knowledge of CPU & SOC architecture/design
- Low-level programming of complex computer systems in C/C++/assembly
- Coding in a scripting language, Perl, Python, Ruby, etc.
- Exposure to object oriented programming concepts
- Knowledge of industry standard interfaces, good understanding of Verilog, Verilog simulator and debug
Benefits For Design Verification Engineer
- Comprehensive medical and dental coverage
- Retirement benefits
- Employee stock programs
- Education reimbursement
- Discretionary restricted stock unit awards
- Employee Stock Purchase Plan with discount
- Discretionary bonuses
- Relocation benefits
