Design Verification Engineer

Global technology company that designs and develops consumer electronics, software, and services.
$143,100 - $264,200
Embedded
Mid-Level Software Engineer
In-Person
3+ years of experience
Hardware

Description For Design Verification Engineer

Apple's wireless silicon development team is seeking a Design Verification Engineer to join their wireless SOC organization. This role is crucial in developing wireless silicon with a focus on energy-efficient design and transformative technologies. As part of a world-class vertically integrated engineering team, you'll work on chip design efforts, collaborating across disciplines including RF/Analog architecture, Systems/PHY/MAC design, and VLSI/RTL design.

The position involves developing and implementing C tests for wireless SoCs verification and power analysis. You'll work in a fast-paced environment, collaborating with cross-functional teams to ensure functional correctness of wireless SoC designs. The role requires expertise in C/C++ programming, Verilog/SystemVerilog, and understanding of digital logic design and chip architecture.

Apple offers a competitive compensation package, including base pay ranging from $143,100 to $264,200, plus opportunities for stock ownership through various programs. The company provides comprehensive benefits including medical and dental coverage, retirement benefits, and education reimbursement.

This is an excellent opportunity for someone with 3+ years of experience who enjoys working in a challenging environment with aggressive schedules. The position offers the chance to impact products used by millions of customers while working with cutting-edge wireless technology at one of the world's leading tech companies.

Last updated 13 days ago

Responsibilities For Design Verification Engineer

  • Work closely with architecture and RTL power designers on defining power vector tests
  • Develop test plan and test environments in C or UVM
  • Develop complex power vector tests for wireless protocol designs in C or assembly
  • Prepare and execute test plans and perform reviews with cross-functional teams
  • Collaborate with Design, Architecture, Power, Silicon Validation, Performance and SW Teams

Requirements For Design Verification Engineer

Python
  • BS with 3+ years relevant experience
  • Experience with C/C++ programming and Verilog/SystemVerilog
  • Understanding of C compilation flow and makefile
  • Knowledge of digital logic design, chip architecture and microarchitecture
  • Ability to develop complex tests or power vectors in assembly or C

Benefits For Design Verification Engineer

Medical Insurance
Dental Insurance
Equity
Education Budget
Relocation Benefits
  • Comprehensive medical and dental coverage
  • Retirement benefits
  • Employee stock programs
  • Education reimbursement
  • Discretionary restricted stock unit awards
  • Employee Stock Purchase Plan with discount
  • Discretionary bonuses
  • Relocation benefits

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