Design Verification Engineer

A technology company that crafts products that enrich people's lives, known for innovative hardware and software solutions.
$121,900 - $183,600
Embedded
Entry-Level Software Engineer
In-Person
5,000+ Employees
Consumer

Description For Design Verification Engineer

Apple, a global leader in technology innovation, is seeking a Design Verification Engineer to join their hardware team in creating groundbreaking products that impact millions of users worldwide. This role presents a unique opportunity to work on cutting-edge hardware verification challenges in a company known for its excellence in product development.

The position focuses on digital verification, where you'll play a crucial role in ensuring the quality and functionality of silicon designs. As a Design Verification Engineer, you'll be responsible for all phases of pre-silicon verification, from establishing methodologies to final tape-out sign-off. You'll work with advanced technologies and tools, including SystemVerilog, UVM, and various verification methodologies.

Your responsibilities will span from developing comprehensive test plans to creating scalable verification environments. You'll be involved in debug processes, coverage analysis, and ensuring the quality of SoC/IP designs. The role requires a strong foundation in hardware verification concepts and tools, with opportunities to work on complex protocols like PCIe and USB.

Apple offers an exceptional compensation package, including competitive base pay, stock options, and comprehensive benefits. You'll be part of a team that values innovation, quality, and attention to detail. The company provides numerous opportunities for professional growth, including educational reimbursement and exposure to cutting-edge technology.

This is an ideal opportunity for someone who enjoys solving complex technical challenges and wants to contribute to products that define the future of technology. You'll work in a collaborative environment with some of the industry's best engineers, with access to state-of-the-art tools and resources. The role offers both technical challenges and career growth opportunities in one of the world's most innovative companies.

Last updated a day ago

Responsibilities For Design Verification Engineer

  • Establish DV methodology and test-plan development
  • Develop verification environment including stimulus and checkers
  • Ensure bug-free first silicon for part of the SoC / IP
  • Develop detailed test and coverage plans
  • Execute verification plans including design bring-up
  • Debug test failures
  • Develop block, IP and SoC level test-benches
  • Track and report DV progress using metrics

Requirements For Design Verification Engineer

Python
Linux
  • Bachelor of Science degree with meaningful experience or internships
  • Deep knowledge of SystemVerilog and UVM
  • Deep knowledge in developing scalable and portable test-benches
  • Experience with verification methodologies and tools
  • UVM knowledge, C/C++ level knowledge
  • Experience with serial protocols (PCIe, USB) and parallel protocols (DDR)
  • Basic knowledge of formal verification methodology
  • Experience with power-aware (UPF) verification methodology
  • Knowledge of scripting languages (Python, Perl, TCL)

Benefits For Design Verification Engineer

Medical Insurance
Dental Insurance
Education Budget
Equity
Relocation Benefits
  • Comprehensive medical and dental coverage
  • Retirement benefits
  • Employee stock programs
  • Educational reimbursement
  • Discretionary restricted stock unit awards
  • Employee Stock Purchase Plan with discount
  • Discretionary bonuses
  • Relocation benefits
  • Product discounts
  • Free services

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