Emulation Verification Engineer
Description For Emulation Verification Engineer
Apple is seeking an Emulation Verification Engineer to join their design verification team, focusing on creating, deploying, and supporting sophisticated emulation environments. This role is crucial in using Emulation for verification of large SoCs and involves working with cutting-edge hardware products. The position offers an opportunity to work at the center of chip design efforts, collaborating with Architecture, Design, and SW teams.
The role demands expertise in hardware verification, particularly in working with emulation platforms like Palladium. You'll be responsible for porting designs to the emulation platform, developing verification environments, and ensuring thorough testing of complex SoCs. The ideal candidate will bring strong technical skills in SystemVerilog, UVM, and hardware verification methodologies.
At Apple, you'll be part of a team that has reinvented entire industries with their hardware products. The company offers comprehensive benefits, including medical coverage, stock options, and educational support. The base salary range of $175,800 to $312,200 reflects the role's senior nature and impact. This is an excellent opportunity for experienced verification engineers who want to work on innovative products that reach millions of customers.
The position offers growth potential within Apple's dynamic environment, where new insights regularly transform into extraordinary products. You'll be working in Cupertino, at the heart of Apple's innovation center, contributing to the next generation of hardware products while collaborating with world-class engineers and architects.
Responsibilities For Emulation Verification Engineer
- Collaborate with Architecture, Design, DV, Silicon Validation, Power and SW teams to bring up large SoCs on emulation platform
- Develop/apply synthesizable monitors/checkers, stimulus on emulation platform
- Prepare and complete test plans and perform reviews with multi-functional teams
- Perform low power testing on emulation platform
- Develop code for Design and verification using Verilog/System Verilog/UVM
- Develop random stimulus infrastructure by reusing existing UVM simulation constraints
Requirements For Emulation Verification Engineer
- BS + 10 years relevant industry experience
- Understanding of tool flow from RTL to Emulation
- Good understanding of Standard Emulator or FPGA flow
- Experience in writing Synthesize-able SystemVerilog/Verilog code and SystemVerilog assertions
- Experience with System Verilog verification environments including C/C++ DPI, UVM
- Experience with writing and debugging test FW
- Experience with Scripting (Perl/Python/TCL)
- Excellent analytical and debug skills
Benefits For Emulation Verification Engineer
- Comprehensive medical and dental coverage
- Retirement benefits
- Employee stock programs
- Educational expense reimbursement
- Discretionary bonuses
- Commission payments
- Relocation benefits
- Employee Stock Purchase Plan
- Discounted products and free services
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