Formal Verification Engineer

A leading technology company that designs and manufactures consumer electronics, software, and services.
$175,800 - $312,200
Embedded
Staff Software Engineer
In-Person
5,000+ Employees
10+ years of experience
AI · Hardware

Description For Formal Verification Engineer

Apple's Silicon Technologies group is seeking a Formal Verification Engineer to join their world-class team. This role is crucial in designing and manufacturing next-generation, high-performance, power-efficient processors and system-on-chip (SoC) solutions. As part of the best Formal Verification team globally, you'll be at the heart of SoC design verification efforts, working directly with design teams to ensure Apple's products maintain their exceptional quality standards.

The position involves comprehensive formal verification for various design blocks and IPs, including CPU, Cellular and Connectivity IP, Audio and Image Processing IP, Neural Networks IP, and more. You'll collaborate with Apple Silicon's world-class engineers to develop specifications, verification plans, and innovative solutions for complex design challenges.

This is an exceptional opportunity for someone with strong technical expertise in formal verification and hardware design. You'll be working on technology that directly impacts millions of customers worldwide, ensuring Apple's devices continue to deliver the seamless experience they're known for. The role offers competitive compensation, comprehensive benefits, and the chance to work with cutting-edge technology at one of the world's most innovative companies.

The ideal candidate will combine technical excellence with strong interpersonal skills, bringing both expertise in formal verification methodologies and the ability to collaborate effectively with diverse teams. This position offers the unique opportunity to influence the development of future Apple products while working with some of the industry's best minds in silicon design and verification.

Last updated 4 days ago

Responsibilities For Formal Verification Engineer

  • Develop formal micro-architecture specification with SOC and IP design engineers
  • Develop comprehensive formal verification test plans
  • Prove properties of the design and find design bugs
  • Create solutions for verifying complex design micro-architectures
  • Develop reusable and optimized formal models and verification code base
  • Architect correct-by-construction design methodologies
  • Complete formal verification for single or multiple design blocks and IP's

Requirements For Formal Verification Engineer

  • BS degree with minimum 10 years of relevant industry experience in silicon validation software engineering
  • Experience with VLSI and digital logic design and verification techniques
  • Knowledge of formal methods and their application to hardware
  • Proficiency in scripting languages with excellent debugging skills
  • Knowledge of temporal logic assertion-based languages (SVA or PSL)
  • Experience with EDA formal tools
  • Knowledge in interpreting hardware specifications
  • Excellent interpersonal skills

Benefits For Formal Verification Engineer

Medical Insurance
Dental Insurance
401k
Equity
Education Budget
Relocation Benefits
  • Comprehensive medical and dental coverage
  • Retirement benefits
  • Employee stock programs
  • Educational expense reimbursement
  • Discretionary bonuses
  • Relocation benefits
  • Employee Stock Purchase Plan
  • Discounted products and free services

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