Mixed-Signal Model Validation Engineer
Description For Mixed-Signal Model Validation Engineer
At Apple, we work every single day to craft products that enrich people's lives. This role presents an exciting opportunity for a Mixed-Signal Model Validation Engineer to join our hardware team. The position combines circuit design expertise with verification methodologies, perfect for those early in their chip design career.
As a Mixed-Signal Model Validation Engineer, you'll be responsible for verifying mixed-signal behavioral models written in SystemVerilog. Your work will involve creating sophisticated testbenches, performing functional testing, and implementing assertions to ensure model accuracy. You'll work with cutting-edge technology and collaborate with experts in circuit design, behavioral modeling, and design verification.
The role offers a unique opportunity to build a strong foundation in full custom analog and high-speed digital circuits. You'll gain hands-on experience with hybrid simulation methods and various verification flows used in full custom designs. Your contributions will directly impact the quality and reliability of Apple's innovative hardware products.
Key responsibilities include:
- Verifying mixed-signal behavioral models using SystemVerilog
- Creating and maintaining self-checking testbenches
- Performing functional testing against specifications
- Implementing assertions for illegal condition detection
- Setting up static flows for formal logical equivalence
- Contributing to flow automation and streamlining
The position offers competitive compensation ($143,100 - $264,200) and comprehensive benefits including medical/dental coverage, retirement benefits, stock programs, and education reimbursement. Join Apple's hardware team and be part of creating the next generation of groundbreaking products that enrich people's lives.
This role is perfect for someone with a strong technical background who wants to grow their career in chip design while working on challenging problems that no one has solved yet. You'll be part of a collaborative team environment where innovation and attention to detail are highly valued.
Responsibilities For Mixed-Signal Model Validation Engineer
- Verifying mixed-signal behavioral models written in SystemVerilog
- Creating self-checking testbenches to simulate models against circuits
- Functional testing of models against specifications
- Creating assertions to flag illegal operating conditions
- Setting up and running static flows like formal logical equivalence, linting, and timing checks
- Contributing to streamlining and automation of flows across mixed-signal design teams
Requirements For Mixed-Signal Model Validation Engineer
- Bachelor's degree with minimum 3 years of relevant experience
- Excellent knowledge of SystemVerilog and Assertions
- Ability to read custom circuit schematics and understand functionality
- Solid understanding of logic/SPICE simulations and SPICE/HDL co-simulations
- Excellent knowledge of digital logic gates, clocking and state elements
- Basics of passive and active circuit elements, voltage and current sources, and analog blocks
Benefits For Mixed-Signal Model Validation Engineer
- Medical Insurance
- Dental Insurance
- Vision Insurance
- 401k
- Education Budget
- Equity
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