Mixed-Signal Verification Engineer
Description For Mixed-Signal Verification Engineer
Apple's wireless silicon development team is seeking a Mixed-Signal Verification Engineer to join their growing organization. This role is part of the wireless SOC team, which handles all aspects of wireless silicon development with a focus on energy-efficient design and innovative technologies. The position offers an opportunity to work with a world-class, vertically integrated engineering team spanning various disciplines including RF/Analog architecture, Systems/PHY/MAC design, and VLSI/RTL design.
The role involves verifying RF/Mixed-Signal blocks and SOCs using SystemVerilog to create testbenches, checkers, models, and tests. You'll be responsible for building and executing test plans to meet project schedules and metric requirements. The position requires strong technical skills in Mixed Signal Verification and Real Numbered Modeling of Mixed Signal Systems, along with expertise in building Mixed-Signal testbenches and debugging.
As part of Apple's team, you'll receive comprehensive benefits including medical and dental coverage, retirement benefits, and the opportunity to become an Apple shareholder through various stock programs. The company offers a collaborative environment where you'll work with cross-functional teams and contribute to cutting-edge technology development.
This is an excellent opportunity for someone who thrives in a fast-paced environment, enjoys technical challenges, and wants to be part of a team that's transforming user experiences through innovative hardware solutions. The role offers competitive compensation, professional growth opportunities, and the chance to work on products that impact millions of users worldwide.
Responsibilities For Mixed-Signal Verification Engineer
- Review specifications and collaborate with Design Team to extract features, define and execute verification plan
- Develop top/block level Mixed Signal and Digital testbench and generate directed/constrained random tests in UVM framework
- Build and reuse real numbered analog behavioral models of Analog and Mixed Signal Circuits
- Build and reuse monitors and checkers for RF, Mixed-Signal and Digital blocks
- Debug failures, fix testbench/model/checker issues, manage bug tracking, and analyze and close coverage
- Write scripts for automation of flow
- Improve Mixed Signal verification methodology
Requirements For Mixed-Signal Verification Engineer
- BS degree is required
- Experience in UVM methodology and HDL (System Verilog, Verilog) for verification
- Understanding of common analog/RF blocks and circuits
- Experience with signal processing using Python or Matlab
- Experience with Virtuoso Composer, ADE and HED
- Ability to work well in a team and be productive under aggressive schedules
Benefits For Mixed-Signal Verification Engineer
- Comprehensive medical and dental coverage
- Retirement benefits
- Employee stock programs
- Discounted products and free services
- Education reimbursement
- Discretionary bonuses
- Relocation assistance
- Employee Stock Purchase Plan
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