Physical Design Engineer
Description For Physical Design Engineer
Apple is seeking a Physical Design Engineer to join their Hardware team in Beaverton, Oregon. This role offers a unique opportunity to work on cutting-edge products that impact millions of customers worldwide. As a Physical Design Engineer, you'll be at the heart of PHY design efforts, collaborating with architecture, CAD, timing, and logic design teams. The position involves comprehensive responsibilities in physical design, from RTL to final GDSII delivery.
The role requires expertise in generating block/chip level timing constraints, building chip floor-plans, and developing clock network guidelines. You'll be responsible for block-level place and route operations, ensuring designs meet timing, area, and power constraints. The position involves working with ECOs for various violations and running physical design verification flows.
The ideal candidate should possess a Bachelor's degree in Electrical Engineering with 3+ years of experience, demonstrating deep knowledge in PHY and SOC designs. Strong understanding of industry standards in Physical Design, including floor-planning and place & route, is essential. Experience with power-grid specifications, physical verification, and scripting languages like Perl/Tcl is crucial.
Apple offers a collaborative environment where you'll work with cutting-edge technology and contribute to products used by millions globally. This is an excellent opportunity for someone passionate about physical design and eager to impact next-generation Apple products. The role combines technical expertise with innovative problem-solving, making it ideal for engineers who thrive on complex challenges and want to be part of a world-class hardware team.
Responsibilities For Physical Design Engineer
- Generate block/chip level static timing constraints
- Build full chip floor-plan including pin placement, partitions and power grid
- Develop and validate high performance low power clock network guidelines
- Perform block level place and route and close the design to meet timing, area and power constraints
- Generate and Implement ECOs to fix timing, noise and EM IR violations
- Run Physical Design verification flow at chip/block level
- Provide guidelines to fix LVS/DRC violations to other designers
- Participate in establishing CAD and physical design methodologies
- Assist in flow development for chip integration
Requirements For Physical Design Engineer
- Bachelors of Science in Electrical Engineering
- Deep design experience in high PHY and/or SOC designs
- Knowledge about industry standards and practices in Physical Design
- Experience in developing and implementing Power-grid and Clock specifications
- Strong understanding of Physical construction, Integration and Physical Verification
- Knowledge of Basic SoC Architecture and HDL languages like Verilog
- Understanding of scripting languages such as Perl/Tcl
- Understanding of Physical Design Verification methodology
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