Physical Synthesis CAD Engineer

As a Physical Synthesis CAD Engineer at Apple, you'll be part of the Silicon Technologies group, working on designing and manufacturing next-generation, high-performance, power-efficient processors and system-on-chip (SoC) solutions. Your role will involve developing, improving, and supporting the implementation flow from RTL through GDS signoff, with a focus on improving physical synthesis techniques through innovative scripts, flows, and automation.

Key responsibilities include:

• Developing and improving existing flows for Physical Synthesis and DFT Implementation
• Supporting multiple design teams and collaborating with cross-functional teams to solve key physical synthesis challenges
• Working with other flows like Logic Equivalence, Static Timing Analysis, and Low Power (UPF) Implementation
• Collaborating with tool vendors to resolve tool and flow issues

This role offers an opportunity to contribute to the technology that powers Apple's beloved devices, ensuring they can efficiently handle tasks that millions of users rely on daily. You'll be at the forefront of crafting and building the technology that fuels Apple's innovative products and services.

Required skills and qualifications:

• Experience with TCL, Python, or Perl scripting languages
• Knowledge of Logic design fundamentals
• Experience with Synthesizable System Verilog RTL
• BS degree (minimum)

Preferred qualifications:

• Knowledge or experience with industry-standard Logic Synthesis tools like Fusion Compiler or Genus
• Exposure to static timing analysis and logic equivalence tools
• Experience writing synthesizable RTL code
• Proficiency with TCL, Python, or Perl scripting languages

Join Apple's team and contribute to the development of cutting-edge technology that impacts millions of users worldwide.