PLL/Clocking Design Engineer

Apple is a technology company that revolutionizes the way people live across the globe with innovative products.
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Senior Software Engineer
In-Person
5,000+ Employees
5+ years of experience
AI · Consumer · Enterprise SaaS

Description For PLL/Clocking Design Engineer

At Apple, our products are revolutionizing the way people live across the globe. Within our Analog-Mixed/Signal group, your role will be crucial in pushing the boundaries of what our technology can achieve. We are dedicated to crafting high-quality, innovative hard IPs that surpass the ordinary, adjusting to the escalating complexity of SOC/PHY designs and multiplying projects within tight production schedules. Our environment thrives on these challenges, fueled by a team of exceptional individuals passionate about continual learning and making a substantial impact.

In this role, you will leverage your expertise to develop cutting-edge frequency synthesizers for a variety of applications, including Compute, SoC, SerDes, and Cellular technologies. Your work will directly contribute to maintaining Apple's leadership in innovation and market presence, setting new standards in the tech industry.

Key Responsibilities and Qualifications:

  • Develop PLL/FLL and frequency synthesis architecture and circuit design, including digital and analog approaches, DCO/VCO design (both RO and LC), Fractional-N, SSC, Spur and Jitter cancellation techniques.
  • Apply knowledge of band gaps, bias circuits, op-amps, LDOs, feedback and compensation techniques.
  • Demonstrate deep understanding of clocking fundamentals, phase noise, jitter analysis, budgeting, and feedback loop dynamics.
  • Develop System Verilog models and perform behavioral simulations to explore new architectural performance and impact on loop dynamics.
  • Focus on understanding problems and their systemic impacts, ensuring thoroughness in problem-solving.
  • Demonstrate innovation, self-directed learning, leadership skills, and a growth mindset.
  • Collaborate effectively in a team environment and utilize industry-standard design tools.

If you excel in dynamic settings, relish collaborative problem-solving, and seek to make a societal impact through your work, you might be the ideal candidate for our team. At Apple, you'll join a culture that encourages you to take ownership of your career, supported by colleagues committed to making a difference.

Last updated 2 months ago

Responsibilities For PLL/Clocking Design Engineer

  • Develop cutting-edge frequency synthesizers for Compute, SoC, SerDes, and Cellular technologies
  • Design and implement PLL/FLL and frequency synthesis architectures
  • Perform behavioral simulations and explore new architectural performance
  • Contribute to maintaining Apple's leadership in innovation and market presence
  • Collaborate with team members on complex projects
  • Utilize industry-standard design tools

Requirements For PLL/Clocking Design Engineer

  • BSEE required or years of relevant experience. MSEE preferred
  • Proficiency in PLL/FLL and frequency synthesis architecture and circuit design
  • Knowledge of band gaps, bias circuits, op-amps, LDOs, feedback and compensation techniques
  • Understanding of clocking fundamentals, phase noise, jitter analysis, budgeting, and feedback loop dynamics
  • Skills in developing System Verilog models and performing behavioral simulations
  • Attention to detail and problem-solving skills
  • Innovation and self-directed learning abilities
  • Strong teamwork and collaboration skills

Interested in this job?

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