PLL/Clocking Design Engineer
Description For PLL/Clocking Design Engineer
At Apple, we're revolutionizing global technology through our Analog-Mixed/Signal group, where you'll play a crucial role in advancing our technological boundaries. We specialize in creating high-quality, innovative hard IPs that exceed expectations, adapting to increasingly complex SOC/PHY designs within strict production timelines. As a PLL/Clocking Design Engineer, you'll be at the forefront of developing cutting-edge frequency synthesizers for various applications, including Compute, SoC, SerDes, and Cellular technologies. Your expertise will directly contribute to maintaining Apple's industry leadership and innovation standards.
The role demands deep technical knowledge in PLL/FLL architecture, circuit design, and clocking fundamentals. You'll work with advanced technologies, developing System Verilog models and performing behavioral simulations. The position requires exceptional attention to detail, strong problem-solving abilities, and outstanding teamwork skills.
We offer an environment that encourages career ownership and continuous learning, surrounded by passionate professionals dedicated to making a difference. Your work will directly impact Apple's product innovation and market leadership, setting new standards in the tech industry. If you're driven by challenges, collaborative problem-solving, and the desire to make a meaningful societal impact, this role presents an exceptional opportunity to contribute to groundbreaking technological advancements at one of the world's most innovative companies.
Responsibilities For PLL/Clocking Design Engineer
- Develop cutting-edge frequency synthesizers for Compute, SoC, SerDes, and Cellular technologies
- Contribute to maintaining Apple's leadership in innovation
- Work on high-quality, innovative hard IPs
- Collaborate with team members on complex SOC/PHY designs
Requirements For PLL/Clocking Design Engineer
- BSEE with at least 10 years of relevant experience
- Demonstrated proficiency in PLL/FLL and frequency synthesis architecture and circuit design
- Knowledge of band gaps, bias circuits, op-amps, LDOs, feedback and compensation techniques
- Deep understanding of clocking fundamentals, phase noise, jitter analysis
- Skills in developing System Verilog models and performing behavioral simulations
- Ability to design/debug RTL
- Strong attention to detail and problem-solving skills
- Outstanding teamwork capabilities
- Experience with industry-standard design tools
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