Power UPF Methodology Engineer
Description For Power UPF Methodology Engineer
Apple's Digital Design Engineering group is seeking a Power UPF Methodology Engineer to join their silicon design team. This role is crucial in designing state-of-the-art ASICs and driving transistor-level power ERC sign-off and power intent-UPF implementation & verification on mobile SOCs. You'll be at the center of SOC design efforts, collaborating across teams to deliver functional products to millions of customers.
The position offers an exciting opportunity to work with cutting-edge technology in mobile SOC design, where you'll develop and implement power verification methodologies for next-generation products. You'll be responsible for critical tasks including mixed signal IP power ERC verification, power intent implementation, and framework development for new projects.
Working at Apple means joining a team that values innovation and technical excellence. The role offers competitive compensation, comprehensive benefits, and the chance to contribute to products used by millions globally. You'll have opportunities for professional growth through education reimbursement and collaboration with industry experts.
The ideal candidate will combine technical expertise in ASIC design methodology with strong communication skills, as you'll work across multiple teams. This role is perfect for someone passionate about power optimization in silicon design and eager to impact the future of mobile technology at one of the world's leading tech companies.
Responsibilities For Power UPF Methodology Engineer
- Drive Mixed signal IP power ERC and power intent verification
- Drive coverage of power intent across static and dynamic checking methodologies
- Define and develop power ERC framework for new projects
- Bring up power intent checking flows on new projects
- Drive power intent & power ERC sign-off for tape-out
- Liaison with CAD and physical design verification team for debugging
- Develop and support transistor level power ERC sign-off for digital and mixed signal designs
Requirements For Power UPF Methodology Engineer
- Bachelor's degree in relevant field
- Minimum 3 years of relevant industry experience
- Experience in ASIC design methodology with emphasis on power definition
- Knowledge of scripting languages (Tcl, Perl, Python)
- Familiar with Caliber based ERC flows
- Familiar with basic circuit & layout fundamentals
- Strong communication skills
- Familiar with entire RTL2GDS flow
Benefits For Power UPF Methodology Engineer
- Comprehensive medical and dental coverage
- Retirement benefits
- Employee stock programs
- Discounted products and free services
- Education reimbursement
- Discretionary bonuses
- Relocation benefits
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