Power UPF Methodology Engineer

A leading technology company that designs and develops consumer electronics, software, and services.
Backend
Mid-Level Software Engineer
In-Person
5,000+ Employees
3+ years of experience
AI · Consumer

Description For Power UPF Methodology Engineer

Join Apple's Digital Design Engineering group and be at the forefront of crafting revolutionary solutions for state-of-the-art ASICs. As a Power UPF Methodology Engineer, you'll be central to our SOC design effort, working on transistor level power ERC sign-off and power intent-UPF implementation & verification for mobile SOCs. You'll collaborate with cross-functional teams to bring innovative products to millions of customers.

The role offers an exciting opportunity to work with cutting-edge technology in hardware design, focusing on power optimization and verification. You'll be responsible for developing and supporting transistor level power ERC sign-off for digital and mixed signal designs, driving full-chip level sign-off, and expanding power sign-off methodology for next-generation mobile products.

You'll be part of a dynamic team that values innovation and technical excellence, working in an environment that encourages collaboration and creative problem-solving. This position combines technical depth in power design methodology with the opportunity to impact Apple's future products. The role requires strong technical skills in ASIC design, power analysis, and verification, along with excellent communication abilities to work effectively across teams.

This is an ideal opportunity for someone passionate about hardware design who wants to make a significant impact on next-generation mobile technologies. You'll have the chance to work with state-of-the-art tools and methodologies while contributing to products that millions of people use daily. The role offers growth opportunities and the chance to work with some of the industry's best engineers in a company known for innovation and excellence.

Last updated 7 days ago

Responsibilities For Power UPF Methodology Engineer

  • Drive Mixed signal IP power ERC and power intent verification
  • Drive coverage of power intent across static and dynamic checking methodologies
  • Define and develop power ERC framework for new projects
  • Bring up power intent checking flows on new projects
  • Drive power intent & power ERC sign-off for tape-out
  • Liaison with CAD and physical design verification team for debugging power ERC and power intent flow issues

Requirements For Power UPF Methodology Engineer

Python
  • Bachelor's degree in relevant field
  • Experience in ASIC design methodology with emphasis on power definition
  • Experience in ASIC design flows and custom IP design flows
  • Knowledge of basic circuit & layout fundamentals
  • Familiarity with Caliber based ERC flows
  • Knowledge of scripting languages (Tcl, Perl, Python)
  • Strong communication skills
  • Familiarity with power intent definition, implementation and verification flows
  • Familiarity with power analysis and optimization methods
  • Familiarity with RTL2GDS flow

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