RFIC - PLL Design Engineer

As an RFIC-PLL Designer at Apple, you'll be part of the wireless RFIC team responsible for architecting, designing, and validating radio transceivers integrated into sophisticated wireless SoCs. You'll work on groundbreaking projects that push the limits of wireless technology, collaborating with multi-functional teams to define radio features and drive innovation.

Key responsibilities include:

• Leading the design of radio transceiver chains, including analog PLLs, digital PLLs, and other critical components
• Driving radio KPI (power, area, performance) to meet product requirements
• Collaborating with RF Systems on block-level and high-level specifications
• Designing RF and Analog loopbacks for calibration and compensation
• Working on Co-Existence scenarios and meeting CoEx requirements
• Leading floorplan layout and verification for successful tape-outs
• Providing design versus silicon measurements correlation

You'll be at the center of a wireless SoC design group with a critical impact on Apple's groundbreaking wireless connectivity solutions, which are integrated into hundreds of millions of products worldwide.

Requirements:

• BS degree with 10+ years of relevant industry experience (MSEE or PhD preferred)
• Solid experience in RF/analog and mixed-signal design in RF CMOS
• Expertise in fractional N Synthesizers, Digital PLLs, Analog PLLs, and LO-Gen
• Hands-on experience with various design components and techniques
• Proficiency in tools like Cadence Virtuoso, Spectre RF, Matlab, and EM simulation
• Familiarity with mixed-signal mode verification methodology

This role offers a competitive base pay range of $166,600 to $296,300, along with additional benefits such as stock options, comprehensive health coverage, and educational reimbursement opportunities. Join Apple's innovative team and contribute to shaping the future of wireless technology!