SoC Physical Design Engineer, PnR
Description For SoC Physical Design Engineer, PnR
We are seeking a seasoned Physical Design technical leader with deep expertise in high-performance & low-power design for our team at Apple. In this highly visible role, you will work closely with cross-functional teams to develop efficient chip and IP physical architecture, considering physical design constraints early in the design cycle.
As a SoC Physical Design Engineer, you'll be responsible for comprehensive physical design implementation, from RTL2GDS including PnR, bump/RDL, STA, physical verification, EMIR, and sign-off. Your expertise will be crucial in driving methodologies and best practices to streamline physical design work and develop robust guidelines.
The ideal candidate will have extensive experience with large SOC designs exceeding 20M gates and frequencies over 1GHZ, along with a proven track record of successful tapeouts in deep submicron technology. You'll need strong technical skills combined with excellent interpersonal abilities to collaborate effectively with cross-functional teams.
This role offers the opportunity to work on cutting-edge technology at Apple, where you'll contribute to developing next-generation hardware solutions. You'll be part of a team that values innovation, technical excellence, and attention to detail, working in an environment that encourages creativity and professional growth.
Responsibilities For SoC Physical Design Engineer, PnR
- Responsible for all aspects of physical design implementation from RTL2GDS including PnR, bump/RDL, STA, physical verification, EMIR, sign-off
- Collaborate to drive methodologies and best-known methods to streamline PD work
- Develop guidelines and checklists
- Serve as primary technical contact for focus area
- Solve challenging timing closure issues, area & power optimization
Requirements For SoC Physical Design Engineer, PnR
- BS degree
- 3+ years of relevant industry experience
- Knowledge in partition level P&R implementation
- Understanding of PD construction & analysis flows and methodology
- Strong interpersonal skills
- Experience with recent successful tapeouts in deep submicron technology
- Experience with large SOC designs (>20M gates) with frequencies over 1GHZ
- Ability to execute to stringent schedule & die size requirements
- Experience with industry standard tools
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