SoC Physical Design Engineer, PnR

A leading technology company that creates innovative products, services, and customer experiences.
$121,900 - $183,600
Embedded
Entry-Level Software Engineer
In-Person
5,000+ Employees
Hardware

Description For SoC Physical Design Engineer, PnR

Apple is seeking a SoC Physical Design Engineer to join their Hardware team in delivering groundbreaking products. This role puts you at the center of design effort, collaborating with architecture, CAD, timing, and logic design teams. You'll have a critical impact on delivering best-in-class designs for highly complex SOCs utilizing innovative process technology.

The position requires expertise in chip architecture, back-end chip design flow, physical synthesis, floor-planning, place and route (PnR), power grid, timing (STA), and physical design verification (DRC/LVS). You'll work directly with logic design teams to understand partition architecture and drive physical aspects early in the design cycle.

At Apple, innovation is the norm, and you'll be part of a team that has reinvented entire industries. The company offers comprehensive benefits, including medical coverage, retirement benefits, and stock programs. You'll have opportunities for professional growth through educational reimbursement and hands-on experience with cutting-edge technology.

The role offers competitive compensation with a base pay range of $121,900 to $183,600, plus additional benefits and stock options. Apple's commitment to leaving the world better than they found it, combined with their track record of creating extraordinary products, makes this an exciting opportunity for someone passionate about hardware design and innovation.

Last updated 18 hours ago

Responsibilities For SoC Physical Design Engineer, PnR

  • Working with logic design team to understand partition architecture
  • Completing netlist to GDS2 implementation for partition(s)
  • Timing, physical and electrical verification, and driving signoff closure
  • Resolve and improve design and flow issues related to physical design
  • Physical implementation of design partition(s) from netlist to tapeout

Requirements For SoC Physical Design Engineer, PnR

Python
  • BS degree minimum
  • Basic understanding of logic gates
  • Experience with Verilog, VHDL, Python, Perl, TCL and/or SPICE (preferred)
  • Strong teamwork skills (preferred)
  • Previous internship/co-op, project work or relevant coursework in computer architecture, VLSI, design, logic design, or circuit design (preferred)

Benefits For SoC Physical Design Engineer, PnR

Medical Insurance
Dental Insurance
401k
Equity
Education Budget
Relocation Benefits
  • Comprehensive medical and dental coverage
  • Retirement benefits
  • Employee stock programs
  • Educational expense reimbursement
  • Discretionary bonuses
  • Relocation assistance
  • Employee discount on products
  • Free services

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