SoC Physical Design Engineer, PnR
Description For SoC Physical Design Engineer, PnR
We are seeking a seasoned Physical Design technical leader at Apple for our Hardware team in Austin. This role requires deep expertise in high-performance & low-power design. As a SoC Physical Design Engineer, you will work in a highly visible position, collaborating closely with cross-functional teams to develop efficient chip and IP physical architecture while considering physical design constraints early in the design cycle.
The role involves comprehensive responsibility for physical design implementation, from RTL2GDS including PnR, bump/RDL, STA, physical verification, EMIR, and sign-off. You'll be instrumental in driving methodologies and best practices to optimize PD workflows and establish robust guidelines. As the primary technical contact for your focus area, you'll tackle complex challenges in timing closure, area optimization, and power efficiency.
The ideal candidate brings 10+ years of industry experience, with proven success in deep submicron technology tapeouts and large SOC designs exceeding 20M gates at 1GHz+ frequencies. Your expertise in partition level P&R implementation, including floorplanning, clock & power distribution, and verification, will be crucial. Strong interpersonal skills and the ability to execute against stringent schedules and die size requirements are essential.
Join Apple's innovative hardware team and contribute to cutting-edge technology development in a collaborative environment that values technical excellence and creative problem-solving. This position offers the opportunity to work on challenging projects that push the boundaries of semiconductor design while being part of a company known for its groundbreaking products and technologies.
Responsibilities For SoC Physical Design Engineer, PnR
- Responsible for all aspects of physical design implementation from RTL2GDS including PnR, bump/RDL, STA, physical verification, EMIR, sign-off
- Collaborate to drive methodologies and best-known methods to streamline PD work
- Develop guidelines and checklists
- Serve as primary technical contact for focus area
- Solve challenging timing closure issues, area & power optimization
Requirements For SoC Physical Design Engineer, PnR
- BS degree
- 10+ years of relevant industry experience
- Knowledge of partition level P&R implementation
- Experience with floorplanning, clock & power distribution, timing closure
- Knowledge of PD construction & analysis flows and methodology
- Strong interpersonal skills
- Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ
- Experience with industry standard tools
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