SoC Physical Design Engineer, Top Level
Description For SoC Physical Design Engineer, Top Level
Apple is seeking a Principal SoC Physical Design Engineer to join their Hardware team in a highly visible role. This position offers an opportunity to work on groundbreaking Apple products, implementing complete chip designs from netlist to tapeout. The role combines technical expertise with leadership responsibilities, requiring deep knowledge of ASIC integration and SoC design.
The ideal candidate will collaborate with front-end teams to drive physical aspects of chip architecture early in the design cycle. They will be responsible for establishing and implementing methodologies, managing place and route activities, and resolving complex design challenges. This position offers exposure to cutting-edge technology and the chance to work on large-scale SoC designs using innovative sub 7nm technologies.
Working at Apple means joining a company known for innovation and product excellence. The compensation package includes competitive base pay, stock options, comprehensive benefits, and educational support. This role provides an opportunity to contribute to products that impact millions of users worldwide while working with industry-leading professionals in hardware design.
The position offers significant growth potential and the chance to influence future Apple hardware products. You'll be part of a team that values innovation, quality, and technical excellence, working in an environment that encourages creativity and problem-solving. If you're passionate about hardware design and want to be at the forefront of technology, this role offers an exceptional opportunity to make a meaningful impact.
Responsibilities For SoC Physical Design Engineer, Top Level
- Work with FE team to understand chip architecture and drive physical aspects early in design cycle
- Drive methodologies and best known methods to streamline physical design work
- Be a focal point for place and route, drive work among place and route engineers
- Set goals and milestones, plan short and long-term work
- Resolve design and flow issues related to physical design
- Implement complete chip design from netlist to tapeout
Requirements For SoC Physical Design Engineer, Top Level
- BS degree and 10+ years of relevant industry experience
- Experience with ASIC integration including floorplanning, clock and power distribution, global signal planning, I/O planning, and hard IP integration
- Experience with SoC issues (multiple voltage and clock domains, ESD strategies, mixed signal block integration, package interactions)
- Experience integrating IP from internal and external vendors
- Understanding of database management issues
- Experience with floorplanning tools, P&R flows, global timing verification and physical design verification flows
Benefits For SoC Physical Design Engineer, Top Level
- Comprehensive medical and dental coverage
- Retirement benefits
- Employee stock programs
- Educational expense reimbursement
- Discretionary restricted stock unit awards
- Employee Stock Purchase Plan with discount
- Discretionary bonuses
- Relocation benefits
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