At Apple, we work every single day to craft products that enrich people's lives. As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions.
In this highly visible role as a SoC Physical Design Verification Engineer, you will:
- Perform various types of physical verification checks such as LVS, DRC, ANT, and ESD at the chip and block level.
- Collaborate with the CAD/Technology teams for flow bring up and validation.
- Work directly with the implementation team during the entire chip design cycle to drive signoff closure for tapeout.
- Lead schedules and support cross-functional engineering efforts.
- Work on padring, bump, RDL design, and collaborate with the package and floorplan teams.
Minimum Qualifications:
- BS in Electrical/Electronics/Computer Engineering or related field.
- 3+ years of relevant industry experience.
- Direct experience with physical verification flows and methodology through tape out execution.
- Knowledge of all aspects of ASIC physical design.
- Knowledge of place and route design flow methodology.
- Scripting skills to debug flow related issues and make enhancements.
- Experience with industry standard tools for physical verification (e.g., Mentor Calibre, Synopsys ICV).
- Full chip tapeout experience with a track record of successful signoff.
Preferred Qualifications:
- MS in Electrical/Electronics/Computer Engineering or related field.
- Proficient scripting skills and automation experience.
- Layout or floorplan design experience.
- Physical design verification and debug experience including mixed signal and digital IP integrations at block and full-chip hierarchies.
Join our team and be part of crafting and building the technology that fuels Apple's devices, enabling our customers to do all the things they love with their devices!