SoC Power Flow Methodology Engineer

As a Power Flow Methodology Engineer at Apple, you'll be part of the Low Power group within Silicon Technologies. Your role involves developing and enhancing low-power flows for cutting-edge chip design, working on highly visible products used by millions. You'll deliver new automated solutions and capabilities for the Silicon Engineering Power team to build more power-efficient chips.

Key responsibilities include:

• Architecting, implementing, and verifying new low-power design and verification flows
• Crafting low-power methodologies across various future technologies
• Creating flows and tools for power analysis, optimization, and verification
• Communicating with the design team to answer questions and resolve issues

You'll work on:

• RTL construction/verification
• Synthesis
• Place and Route (P&R)

This role offers the opportunity to create solutions for complex challenges and contribute to Apple's next-generation chips. You'll be at the forefront of developing new capabilities in power domains unseen in previous chips.

Requirements:

• BS degree and minimum 3 years of relevant industry experience
• Good understanding of VLSI designs and SOC design flows
• Strong passion for scripting and applying low-power domain-specific knowledge
• Solid background in flow development and/or object-oriented language algorithm design (Python, C++, Java)
• Experience with modern software testing and development practices
• Excellent written and verbal communication skills

Additional skills that are beneficial:

• Knowledge of Tcl/Perl
• Experience with EDA tools
• GUI development experience
• Understanding of low-power concepts such as UPF and low-power design

Join Apple's Hardware team and be part of creating the technology that powers millions of devices worldwide!