SoC Power Grid Integrity Engineer

The Power Circuits & Technology team at Apple is seeking a SoC Power Grid Integrity Engineer intern to join their low-power chip design team. This role is crucial in enabling all-day-battery-life on Apple's phone and watch products. The intern will be responsible for verifying the integrity of the power grid in complex SOC designs and analyzing its timing impact.

Key responsibilities include:

• Analyzing IVD (Instantaneous Voltage Drop) and timing simulation results
• Developing Machine Learning based experimental flows for power integrity analysis
• Exploring new tools and methodologies for power grid integrity
• Investigating the impact of resonance in IVD simulations
• Developing new or improving existing CAD flows

The ideal candidate should have a strong understanding of power grid integrity, reliability, and noise impact on circuit functionality and timing. Experience in ASIC design methodology, spice simulations, library characterization, and scripting is required. Knowledge of Machine Learning fundamentals is also necessary.

This internship offers an opportunity to work with a team that uses a combination of data analysis, low-power chip design, RTL-to-GDS flow methodology, and customized scripting, automation, and visualization to bring innovative low-power design techniques to Apple silicon.

Join Apple's hardware development team and contribute to the next generation of SoCs while gaining valuable experience in a fast-paced, innovative environment.