SoC Power Modeling Engineer

A leading technology company that designs and develops consumer electronics, software, and services.
Embedded
Mid-Level Software Engineer
In-Person
3+ years of experience
AI

Description For SoC Power Modeling Engineer

Join Apple's Silicon Engineering group as a SoC Power Modeling Engineer, where you'll be at the forefront of designing state-of-the-art ASICs integral to many Apple products. This role focuses on modeling power dissipation of various IPs, including AI/ML components, power rails, peak current requirements, and voltage-frequency operating points for next-generation Apple SOCs. You'll collaborate across multiple teams including architecture, design, thermals, PMIC, and system design to optimize power efficiency in leading-edge chips. The position offers unique opportunities to work with hardworking engineers on HW/model correlation efforts of mobile SoC design. You'll be responsible for establishing voltage-frequency design points, modeling power dissipation for customer use-cases, and working closely with lab teams for hardware correlation. This role is perfect for someone passionate about power optimization in silicon design and eager to contribute to innovative products used by millions of customers worldwide. The position combines technical expertise with cross-functional collaboration, making it an exciting opportunity for those interested in advanced chip design and power efficiency optimization.

Last updated 7 days ago

Responsibilities For SoC Power Modeling Engineer

  • Modeling power dissipation and power delivery
  • Establishing voltages for DVFM states of IPs, including Neural Engines, CPUs, Graphics, compute (AI/ML) accelerators, media IPs, caches and fabric
  • Modeling power dissipation for customer use-cases
  • Interacting with Technology team, Silicon Validation, and Product Engineering teams to establish voltage-frequency design points
  • Working with power lab and test teams to correlate models to HW data

Requirements For SoC Power Modeling Engineer

  • Bachelor's degree in relevant field
  • Understanding of SOC power modeling and current demand
  • Understanding of electrical properties of on-die PDN, power gating, package and system power delivery
  • Skills in scripting, data analysis and experience with EDA tools
  • Understanding of VLSI design flow and CMOS technology
  • Extensive background in EE
  • Ability to understand and model thermal control loops and throttling mechanisms
  • Familiarity with physical design tools for power optimization
  • Great teammate and excellent communication skills

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