Join Apple's Silicon Engineering group as a SoC Power Modeling Engineer, where you'll be at the forefront of designing state-of-the-art ASICs integral to many Apple products. This role focuses on modeling power dissipation of various IPs, including AI/ML components, power rails, peak current requirements, and voltage-frequency operating points for next-generation Apple SOCs. You'll collaborate across multiple teams including architecture, design, thermals, PMIC, and system design to optimize power efficiency in leading-edge chips. The position offers unique opportunities to work with hardworking engineers on HW/model correlation efforts of mobile SoC design. You'll be responsible for establishing voltage-frequency design points, modeling power dissipation for customer use-cases, and working closely with lab teams for hardware correlation. This role is perfect for someone passionate about power optimization in silicon design and eager to contribute to innovative products used by millions of customers worldwide. The position combines technical expertise with cross-functional collaboration, making it an exciting opportunity for those interested in advanced chip design and power efficiency optimization.