Timing Design Engineer

At Apple, we work every single day to craft products that enrich people's lives. As a Timing Design Engineer, you will be part of a multifaceted group with the opportunity to craft upcoming products that will delight millions of Apple's customers. You'll be at the center of a PHY design effort, collaborating with architecture, CAD, and logic design teams, with a critical impact on delivering outstanding PHY designs.

As an ASIC STA Engineer, your responsibilities will span all aspects of SoC design in terms of timing. Key responsibilities include:

• Timing sign-off
• STA and sign-off flow development
• Ownership of IP and block level timing constraints for regular and custom timing requirements
• Close interaction with RTL designers to understand design intent and clock structure
• Collaboration with CAD to understand and develop flow
• Working with Physical design team to close and sign-off timing
• Developing ideas and plans to verify timing constraints
• Innovating timing constraints and flow to facilitate timing closure and address potential pessimism or fall outs in timing analysis

The ideal candidate will have:

• Thorough knowledge of ASIC design timing closure flow and methodology
• At least 5+ years of experience in writing ASIC timing constraints and timing closure
• Expertise in STA tools (Primetime) and flow
• Knowledge of timing corners/modes, process variations, and signal integrity related issues
• Hands-on experience in timing/SDC constraints generation and management
• Proficiency in scripting languages (Tcl and Perl)
• Familiarity with synthesis, DFT, and backend related methodology and tools
• Strong communication skills
• Self-motivation and drive to succeed at Apple

This role offers a unique opportunity to work on cutting-edge technology and contribute to products used by millions of people worldwide. Join Apple's Hardware team and be part of shaping the future of technology.