Wireless SOC Design Verification Engineer
Description For Wireless SOC Design Verification Engineer
Apple is seeking a Design Verification Engineer to join their silicon design group, focusing on state-of-the-art Wireless SoCs. This role offers an exciting opportunity to work at the heart of verification efforts for complex SOC architectures. You'll be responsible for pre-silicon RTL verification at both block and top-level SOC, requiring expertise in all areas of SoC Design Verification engineering.
The position involves working with cutting-edge wireless protocols, firmware-hardware interactions, and multi-chip SOC debug architecture. You'll be part of a dynamic team that pushes the boundaries of wireless systems, directly improving product experiences for customers worldwide. The role requires deep understanding of high-efficiency SOC architecture, standard peripherals, and low-power methodologies.
As part of Apple's hardware team, you'll collaborate with multiple product development groups, working on sophisticated IP-level DV environments and implementing best-in-class UVM Testbenches. The position offers exposure to large-scale SOC architecture, various high-speed layered protocols, and advanced verification methodologies.
The compensation package includes a competitive base salary range of $135,400 to $250,600, plus opportunities for stock awards, bonuses, and comprehensive benefits. This is an excellent opportunity for someone with strong verification experience who wants to work on industry-leading wireless technology products at one of the world's most innovative companies.
Responsibilities For Wireless SOC Design Verification Engineer
- Verify complex SOCs and integrate multiple IP-level DV environments
- Craft reusable UVM Testbenches and implement coverage-driven test cases
- Develop coverage-driven verification plans from specifications
- Architect UVM-based reusable test benches and integrate complex multi-instance VIPs
- Work with design, architecture, SW, FW, and external IP delivery teams
- Deliver on Power Management designs using low-power methodologies
- Work closely with DV methodology architects to improve verification flow
Requirements For Wireless SOC Design Verification Engineer
- BS + 3 years of industry experience
- Experience with ASIC DV
- Knowledge of HVL methodology (UVM/OVM) with recent UVM experience
- Experience with formal verification
- Experience taping out large SOC systems with embedded processor cores
- Hands-on verification experience of PCIe, Bus Fabric, NOC, AHB, AXI
- Knowledge of Low Power Verification
Benefits For Wireless SOC Design Verification Engineer
- Comprehensive medical and dental coverage
- Retirement benefits
- Employee stock programs
- Educational expense reimbursement
- Discretionary bonuses
- Relocation benefits
- Employee Stock Purchase Plan
- Discounted products and free services
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