Global leader in purpose-built connectivity solutions for AI and cloud infrastructure, specializing in PCIe, CXL, and Ethernet semiconductor solutions.

Astera Labs, a leading innovator in connectivity solutions for AI and cloud infrastructure, is seeking a Principal Digital Design Engineer to join their team in Bengaluru, India. This role represents an opportunity to work at the cutting edge of semiconductor design, focusing on high-performance controller and bridge design, micro-architecture, and RTL implementation.

The position requires a seasoned professional with 12+ years of experience in digital design, particularly in processor and full chip implementation. You'll be responsible for designing and implementing high-performance digital solutions, working with advanced nodes (16nm and below), and managing complex system integration tasks. The role combines deep technical expertise in RTL development, synthesis, and timing closure with strategic oversight of block-level and full-chip designs.

Astera Labs' Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions with their COSMOS software suite, delivering scalable and customizable architecture for modern data centers. This role offers the opportunity to work with state-of-the-art technology and contribute to solutions that are transforming modern data-driven applications.

The company values diversity and actively encourages applications from people of all backgrounds, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities. The position offers the chance to work with cutting-edge technology while being part of a company that's making significant impacts in the AI and cloud infrastructure space.

Principal Digital Design Engineer role at Astera Labs, focusing on high-performance controller design and RTL implementation for advanced semiconductor solutions.

Principal Digital Design Engineer-SOC

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure.

Astera Labs is seeking a Principal DFT (Design for Test) Engineer to join their DFT Design team. This role involves developing next-generation connectivity products for leading cloud service providers and server/networking OEMs. The position offers exposure to the full product lifecycle, from definition to mass production and end-of-life. 

Key responsibilities include:
- Collaborating with multiple engineering teams
- Working on chip design, verification, and DFT techniques
- Utilizing ATPG tools and running test compression software
- Performing gate-level simulations and static timing analysis

The ideal candidate will have:
- A minimum of a bachelor's degree in computer/electrical engineering (Masters preferred)
- 10+ years of experience in a semiconductor company as a DFT engineer
- Strong knowledge of Verilog, System Verilog, and UVM methodology
- Expertise with commercial test generation tools for large complex designs
- Experience with Mentor Tessent or Synopsys DFT Max and Tetramax tools

This role offers the opportunity to work on cutting-edge connectivity solutions that are transforming modern data-driven applications. The successful candidate will be part of a team that values creativity, innovation, and diverse perspectives.

Astera Labs is committed to fostering an inclusive work environment and encourages applications from people of all backgrounds, including people of color, LGBTQ+ and non-binary individuals, veterans, parents, and individuals with disabilities.

Astera Labs seeks a Principal DFT Engineer to develop next-gen connectivity products for cloud and server/networking industries.

Principal DFT Engineer (Design For Test)

Astera Labs is seeking a Senior Physical Design Engineer to join their team in Bengaluru, India. The ideal candidate will have a strong background in electrical engineering or computer science, with at least 5 years of experience in complex SoC/silicon product development for Server, Storage, and/or Networking applications.

Key responsibilities include:
- Driving multiple complex designs from architecture to GDSII at both full chip and block levels
- Expertise in synthesis, timing closure, and formal verification
- Working with Cadence and/or Synopsys physical design tools/flows
- Collaborating with IP vendors for both RTL and hard-mac blocks

Required skills and qualifications:
- Bachelor's degree in EE / Computer Science (Master's preferred)
- Hands-on knowledge of synthesis, place and route, timing, extraction, and other backend tools for 16nm or less technologies
- Experience with System Verilog/Verilog
- Familiarity with DFT tools and techniques
- Strong scripting skills in Python or Perl

The ideal candidate will have an entrepreneurial mindset, ability to prioritize tasks, and work with minimal supervision. Experience with DFT test coverage, debug, and ECO methodologies is a plus.

Astera Labs offers a dynamic work environment focused on innovation in AI and cloud infrastructure. Join a team that values diversity and is transforming modern data-driven applications.

Senior Physical Design Engineer role at Astera Labs, focusing on complex SoC/silicon product development for AI and cloud infrastructure.

Senior Physical Design Engineer

Astera Labs is seeking a Senior DFT (Design For Test) Engineer to join their DFT Design team. This role involves developing next-generation connectivity products for leading cloud service providers and server/networking OEMs. The position offers exposure to the full product life-cycle and requires close collaboration with various engineering teams.

Key Responsibilities:
- Develop DFT solutions for complex semiconductor designs
- Work on chip design, verification, and test generation
- Collaborate with multiple engineering teams throughout the product lifecycle
- Implement and optimize test compression techniques
- Conduct gate-level simulations and static timing analysis

Required Qualifications:
- Bachelor's degree in Computer Engineering or Electrical Engineering
- 5+ years of experience as a DFT engineer in a semiconductor company
- Expertise in chip design, Verilog, and System Verilog
- Proficiency in UVM methodology and ATPG tools
- Experience with scan insertion tools and test compression software
- Strong knowledge of DFT techniques (JTAG, ATPG, test pattern translation, yield learning, logic diagnosis)
- Familiarity with ATE and commercial test generation tools
- Scripting skills (Perl/Tcl)

Preferred Experience:
- SOC level verification on large designs
- Working with 93k Tester
- Knowledge of IEEE 1500 Standard or IEEE 1687 standard
- Experience with MBIST and LBIST

Astera Labs values diversity and encourages applications from people of color, LGBTQ+ individuals, veterans, parents, and individuals with disabilities. The company offers a competitive salary based on location and experience.

Join Astera Labs to work on cutting-edge connectivity solutions and be part of a team transforming modern data-driven applications.

Senior DFT Engineer role at Astera Labs, developing next-gen connectivity solutions for AI and cloud infrastructure.

Senior DFT Engineer

Astera Labs is seeking a Principal Diagnostic Platform Software Engineer to join their Hardware Engineering team. This role involves building diagnostics and manufacturing software for cutting-edge high-speed datacenter products, from conception to final production. The ideal candidate will have a strong software background with good understanding of hardware design and manufacturing practices.

Key responsibilities include:
- Designing and implementing production-grade diagnostics for high-speed digital boards and ASICs
- Creating manufacturing tests for mass production validation
- Bringing up newly manufactured boards and porting first-level software
- Performing root-cause analysis of reported failures
- Supporting new platform software and hardware features
- Coordinating with the hardware engineering team on schedules and feature delivery
- Participating in design discussions, reviews, and project management
- Mentoring younger team members

The role requires a Bachelor's degree in Computer Science or Computer Engineering (or equivalent experience) and at least 8 years of experience in diagnostics, hardware bring-up, testing, or manufacturing automation. Proficiency in Python and knowledge of modern software development practices are essential.

Preferred qualifications include experience with datacenter-level complex electronic equipment, ability to read schematics/layouts, system debug experience, embedded programming, knowledge of OS internals, and familiarity with interconnecting buses and interfaces such as PCIe, I2C, XAUI, and 10G Ethernet.

Astera Labs values diversity and creativity, actively encouraging applications from people of all backgrounds, including people of color, LGBTQ+ and non-binary individuals, veterans, parents, and individuals with disabilities.

Join Astera Labs to work on innovative connectivity solutions that are transforming modern data-driven applications in the AI and cloud infrastructure space.

Principal Diagnostic Platform Software Engineer role at Astera Labs, focusing on building diagnostics and manufacturing software for high-speed datacenter products.

Astera Labs Engineering Jobs

Global leader in purpose-built connectivity solutions for AI and cloud infrastructure, specializing in PCIe, CXL, and Ethernet semiconductor solutions.