Global leader in purpose-built connectivity solutions for AI and cloud infrastructure

Astera Labs is seeking a Technical Customer Engineering Intern to join their team. This exciting role offers the opportunity to be at the forefront of driving the company's success in the competitive and growing AI Solutions market. As an intern, you'll develop foundational skills needed to drive business growth, engaging actively in understanding customer needs, providing technical solutions, and effectively articulating the value of Astera Labs' products and services.

Key responsibilities include:
1. Understanding customer needs and aligning product offerings
2. Providing technical expertise throughout the sales process
3. Conducting product demonstrations and delivering compelling presentations
4. Collaborating with the sales team to identify new opportunities
5. Developing strong customer relationships
6. Contributing to sales strategies and contract negotiations
7. Working with customers' engineering teams to integrate Astera Labs' semiconductor solutions
8. Collaborating with internal engineering teams to gather product feedback

You'll gain in-depth knowledge of semiconductor products, with a focus on PCI/CXL/Ethernet protocol connectivity solutions. The role involves hands-on learning of AI HW Infrastructure, including server design architecture, rack integration, and silicon development. You'll also prepare to present Astera Labs' product portfolio to customer engineering teams and study customer needs to create product engagement strategies.

This internship provides a unique opportunity to work with cutting-edge technology in the AI and cloud infrastructure space, while developing valuable skills in technical sales, customer relations, and product development. If you're passionate about enabling customer innovation and want to be part of a dynamic team driving the future of connectivity solutions, this internship at Astera Labs could be the perfect fit for you.

Technical Customer Engineering Intern at Astera Labs, focusing on AI and cloud infrastructure connectivity solutions

Sales Engineer Internship

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. We are seeking a Principal Digital Design Engineer-CXL/PCIe with deep expertise in high-performance controller and bridge design, micro-architecture, RTL implementation, and IP integration. The ideal candidate will play a critical role in the development of cutting-edge connectivity solutions.

Key Responsibilities:
- Design and implement high-performance digital solutions, including RTL development and synthesis
- Collaborate with cross-functional teams on IP integration for PCIe/CXL protocols
- Own block-level and full-chip designs from architecture to GDS, focusing on designs at nodes ≤ 16nm
- Ensure timing closure, assess verification completeness, and oversee pre- and post-silicon debug
- Utilize tools from Synopsys/Cadence and apply expertise in UVM-based verification flows

This role offers an opportunity to work on cutting-edge technology in the field of AI and cloud infrastructure connectivity. You'll be part of a team that's transforming modern data-driven applications and contributing to the development of innovative products that are flexible and interoperable.

Join Astera Labs to be at the forefront of connectivity solutions, working with advanced technologies and protocols like PCIe and CXL. This position is ideal for someone who thrives in a collaborative environment, has a strong work ethic, and is passionate about pushing the boundaries of digital design in the semiconductor industry.

Principal Digital Design Engineer for CXL/PCIe at Astera Labs, developing cutting-edge connectivity solutions for AI and cloud infrastructure.

Principal Digital Design Engineer - CXL/PCIe

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure.

Astera Labs is seeking a Principal Digital Design Engineer with deep expertise in high-performance controller and bridge design, micro-architecture, RTL implementation, and IP integration. The ideal candidate will play a critical role in the development of cutting-edge connectivity solutions.

Key Responsibilities:
- Design and implement high-performance digital solutions, including RTL development and synthesis.
- Collaborate with cross-functional teams on IP integration for processor IPS and peripherals
- Deep knowledge of processor boot process and peripheral implementation with boot firmware in mind
- Own block-level and full-chip designs from architecture to GDS, focusing on designs at nodes ≤ 16nm.
- Ensure timing closure, assess verification completeness, and oversee pre- and post-silicon debug.
- Utilize tools from Synopsys/Cadence and apply expertise in UVM-based verification flows

Basic Qualifications:
- Bachelor's in Electronics/Electrical engineering (Master's preferred).
- 12+ years of digital design experience, with 4+ years focused on processor, peripherals and full chip implementation.
- Proven expertise in RTL development, synthesis, and timing closure.
- Experience with front-end design, gate-level simulations, and design verification.
- Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude.

Required Expertise:
- Hands-on experience with processor IP (ARM/ARC)
- Hands-on pre-silicon and post-silicon implementing peripherals for I2C/SPI/UART
- Hands-on experience with complex DMA engines and FW interaction
- Strong proficiency in System Verilog/Verilog and scripting (Python/Perl).
- Experience with block-level and full-chip design at advanced nodes (≤ 16nm).
- Silicon bring-up and post-silicon debug experience.
- Familiarity with Synopsys/Cadence tools and UVM-based design verification.

Preferred Experience:
- Knowledge and experience implementing secure boot and security mechanisms like authentication and attestation is a plus
- Knowledge of system-level design with ARM/ARC/RISC-V processors sub systems
- Understanding of PAD design, DFT, and floor planning.
- Experience with NIC, switch, or storage product development.
- Familiarity with working in design and verification workflows in a CI/CD environment.

Astera Labs values diversity and encourages applications from people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Principal Digital Design Engineer-SOC at Astera Labs, developing cutting-edge connectivity solutions for AI and cloud infrastructure.

Principal Digital Design Engineer-SOC

Astera Labs is seeking a Senior Firmware Verification Engineer to join their team. As a Firmware Verification Engineer at Astera Labs, you will be responsible for verifying the firmware and microcontroller subsystems for Astera Labs' SoC and system products. In this role, you will play a key part in ensuring the quality and reliability of firmware by using both white-box and black-box testing methodologies. You will work closely with the firmware development team to build and execute test cases for specific components, identify bugs, and verify the overall implementation. This role will focus on validating firmware for high-speed interfaces in data center, server, and networking applications.

Key Responsibilities:
- Develop and execute test plans for firmware verification using white-box testing methodologies at the component level (e.g., PCIe, UART, SPI).
- Review code, identify bugs, and thoroughly test various firmware levels, including PHY, PCIe, and security features.
- Collaborate with the development team to ensure proper verification of hardware-software (HW-SW) interfaces on complex SoCs.
- Create automated test scripts using Python and manage test environments to ensure efficiency and accuracy in testing.
- Work with system-level validation and QA teams to ensure comprehensive testing of the entire product lifecycle.

Astera Labs offers a competitive salary range of $120,000 - $190,000 USD, with the final offer based on location, experience, and comparison to similar positions. The company values diversity and encourages applications from people of all backgrounds, including people of color, LGBTQ+ and non-binary individuals, veterans, parents, and individuals with disabilities.

Join Astera Labs and be part of a team that is transforming modern data-driven applications through innovative connectivity solutions.

Senior Firmware Verification Engineer at Astera Labs: Verify firmware and microcontroller subsystems for SoC and system products, focusing on high-speed interfaces in data center applications.

Senior Firmware Verification Engineer

Astera Labs is seeking a Principal DFT (Design for Test) Engineer to join their DFT Design team. This role involves developing next-generation connectivity products for leading cloud service providers and server/networking OEMs. The position offers exposure to the full product lifecycle, from definition to mass production and end-of-life. 

Key responsibilities include:
- Collaborating with multiple engineering teams
- Working on chip design, verification, and DFT techniques
- Utilizing ATPG tools and running test compression software
- Performing gate-level simulations and static timing analysis

The ideal candidate will have:
- A minimum of a bachelor's degree in computer/electrical engineering (Masters preferred)
- 10+ years of experience in a semiconductor company as a DFT engineer
- Strong knowledge of Verilog, System Verilog, and UVM methodology
- Expertise with commercial test generation tools for large complex designs
- Experience with Mentor Tessent or Synopsys DFT Max and Tetramax tools

This role offers the opportunity to work on cutting-edge connectivity solutions that are transforming modern data-driven applications. The successful candidate will be part of a team that values creativity, innovation, and diverse perspectives.

Astera Labs is committed to fostering an inclusive work environment and encourages applications from people of all backgrounds, including people of color, LGBTQ+ and non-binary individuals, veterans, parents, and individuals with disabilities.

Astera Labs seeks a Principal DFT Engineer to develop next-gen connectivity products for cloud and server/networking industries.

Principal DFT Engineer (Design For Test)

Astera Labs is seeking a Senior Physical Design Engineer to join their team in Bengaluru, India. The ideal candidate will have a strong background in electrical engineering or computer science, with at least 5 years of experience in complex SoC/silicon product development for Server, Storage, and/or Networking applications.

Key responsibilities include:
- Driving multiple complex designs from architecture to GDSII at both full chip and block levels
- Expertise in synthesis, timing closure, and formal verification
- Working with Cadence and/or Synopsys physical design tools/flows
- Collaborating with IP vendors for both RTL and hard-mac blocks

Required skills and qualifications:
- Bachelor's degree in EE / Computer Science (Master's preferred)
- Hands-on knowledge of synthesis, place and route, timing, extraction, and other backend tools for 16nm or less technologies
- Experience with System Verilog/Verilog
- Familiarity with DFT tools and techniques
- Strong scripting skills in Python or Perl

The ideal candidate will have an entrepreneurial mindset, ability to prioritize tasks, and work with minimal supervision. Experience with DFT test coverage, debug, and ECO methodologies is a plus.

Astera Labs offers a dynamic work environment focused on innovation in AI and cloud infrastructure. Join a team that values diversity and is transforming modern data-driven applications.

Senior Physical Design Engineer role at Astera Labs, focusing on complex SoC/silicon product development for AI and cloud infrastructure.

Senior Physical Design Engineer

Astera Labs is seeking a Senior DFT (Design For Test) Engineer to join their DFT Design team. This role involves developing next-generation connectivity products for leading cloud service providers and server/networking OEMs. The position offers exposure to the full product life-cycle and requires close collaboration with various engineering teams.

Key Responsibilities:
- Develop DFT solutions for complex semiconductor designs
- Work on chip design, verification, and test generation
- Collaborate with multiple engineering teams throughout the product lifecycle
- Implement and optimize test compression techniques
- Conduct gate-level simulations and static timing analysis

Required Qualifications:
- Bachelor's degree in Computer Engineering or Electrical Engineering
- 5+ years of experience as a DFT engineer in a semiconductor company
- Expertise in chip design, Verilog, and System Verilog
- Proficiency in UVM methodology and ATPG tools
- Experience with scan insertion tools and test compression software
- Strong knowledge of DFT techniques (JTAG, ATPG, test pattern translation, yield learning, logic diagnosis)
- Familiarity with ATE and commercial test generation tools
- Scripting skills (Perl/Tcl)

Preferred Experience:
- SOC level verification on large designs
- Working with 93k Tester
- Knowledge of IEEE 1500 Standard or IEEE 1687 standard
- Experience with MBIST and LBIST

Astera Labs values diversity and encourages applications from people of color, LGBTQ+ individuals, veterans, parents, and individuals with disabilities. The company offers a competitive salary based on location and experience.

Join Astera Labs to work on cutting-edge connectivity solutions and be part of a team transforming modern data-driven applications.

Senior DFT Engineer role at Astera Labs, developing next-gen connectivity solutions for AI and cloud infrastructure.

Senior DFT Engineer

Astera Labs is seeking a Principal Diagnostic Platform Software Engineer to join their Hardware Engineering team. This role involves building diagnostics and manufacturing software for cutting-edge high-speed datacenter products, from conception to final production. The ideal candidate will have a strong software background with good understanding of hardware design and manufacturing practices.

Key responsibilities include:
- Designing and implementing production-grade diagnostics for high-speed digital boards and ASICs
- Creating manufacturing tests for mass production validation
- Bringing up newly manufactured boards and porting first-level software
- Performing root-cause analysis of reported failures
- Supporting new platform software and hardware features
- Coordinating with the hardware engineering team on schedules and feature delivery
- Participating in design discussions, reviews, and project management
- Mentoring younger team members

The role requires a Bachelor's degree in Computer Science or Computer Engineering (or equivalent experience) and at least 8 years of experience in diagnostics, hardware bring-up, testing, or manufacturing automation. Proficiency in Python and knowledge of modern software development practices are essential.

Preferred qualifications include experience with datacenter-level complex electronic equipment, ability to read schematics/layouts, system debug experience, embedded programming, knowledge of OS internals, and familiarity with interconnecting buses and interfaces such as PCIe, I2C, XAUI, and 10G Ethernet.

Astera Labs values diversity and creativity, actively encouraging applications from people of all backgrounds, including people of color, LGBTQ+ and non-binary individuals, veterans, parents, and individuals with disabilities.

Join Astera Labs to work on innovative connectivity solutions that are transforming modern data-driven applications in the AI and cloud infrastructure space.

Principal Diagnostic Platform Software Engineer role at Astera Labs, focusing on building diagnostics and manufacturing software for high-speed datacenter products.

Principal Diagnostic Platform Software Engineer

Astera Labs, a global leader in purpose-built connectivity solutions for AI and cloud infrastructure, is seeking a Software/Firmware Engineer for their Platform (BMC) team. This role is crucial in architecting and developing firmware and microcontroller subsystems for Astera Labs' SoC and systems products.

**Key Responsibilities:**
- Implement major differentiating features of Astera Labs' products through firmware development
- Interface directly with customers to ensure their needs are fully understood
- Develop embedded firmware with multi-path communication channels (serial and in-band mailbox)
- Work on BMC/iDRAC or similar out-of-band development
- Develop software that interacts via serial buses (I2C/CAN/SPI)
- Create drivers, protocol layers, and handler code over serial buses

**Required Qualifications:**
- Bachelor's in EE or Computer Science (Master's preferred)
- Minimum 5 years' experience in complex SoC/silicon products for Server, Storage, and/or Networking applications
- Strong proficiency in C (preferred) or C++
- Experience with MCTP over I2C or PCIe for BMC interactions
- Familiarity with software build environments, SCM (preferably git), and CI workflows
- Hands-on experience with servers and peripherals such as storage and NICs

**Preferred Skills:**
- Knowledge of OpenBMC, BIOS/Host OS/kernel interactions with BMC
- Experience with PLDM/SPDM models and DMTF standards
- Familiarity with RDE and protocol overlay for BMC
- Experience with Linux kernel mode drivers and industry forums like OCP and OpenBMC

This role offers an exciting opportunity to work at the forefront of AI and cloud infrastructure technology. The successful candidate will join a dynamic team committed to innovation and customer-centric solutions. Astera Labs values diversity and encourages applications from all backgrounds.

Salary Range: $140,000 - $220,000 USD, based on experience and location.

Join Astera Labs and be part of transforming modern data-driven applications!

Software/Firmware Engineer for Platform (BMC) at Astera Labs, developing firmware and microcontroller subsystems for SoC and systems products.

Astera Labs Engineering Jobs

Global leader in purpose-built connectivity solutions for AI and cloud infrastructure