Principal DFT Engineer (Design For Test)
Description For Principal DFT Engineer (Design For Test)
Astera Labs is seeking a Principal DFT (Design for Test) Engineer to join their DFT Design team. This role involves developing next-generation connectivity products for leading cloud service providers and server/networking OEMs. The position offers exposure to the full product lifecycle, from definition to mass production and end-of-life.
Key responsibilities include:
- Collaborating with multiple engineering teams
- Working on chip design, verification, and DFT techniques
- Utilizing ATPG tools and running test compression software
- Performing gate-level simulations and static timing analysis
The ideal candidate will have:
- A minimum of a bachelor's degree in computer/electrical engineering (Masters preferred)
- 10+ years of experience in a semiconductor company as a DFT engineer
- Strong knowledge of Verilog, System Verilog, and UVM methodology
- Expertise with commercial test generation tools for large complex designs
- Experience with Mentor Tessent or Synopsys DFT Max and Tetramax tools
This role offers the opportunity to work on cutting-edge connectivity solutions that are transforming modern data-driven applications. The successful candidate will be part of a team that values creativity, innovation, and diverse perspectives.
Astera Labs is committed to fostering an inclusive work environment and encourages applications from people of all backgrounds, including people of color, LGBTQ+ and non-binary individuals, veterans, parents, and individuals with disabilities.
Responsibilities For Principal DFT Engineer (Design For Test)
- Develop next-generation connectivity products for cloud service providers and server/networking OEMs
- Work on the full product lifecycle, from definition to mass production to end of life
- Collaborate closely with all engineering teams, physical design, and functions like back-end testing, manufacturing, defect, and reliability analysis
- Solve problems in a collaborative manner between multiple engineering teams
Requirements For Principal DFT Engineer (Design For Test)
- Minimum of bachelor's degree in computer engineering/electrical engineering, Masters preferred
- 10+ years of experience in a semiconductor company as a DFT engineer
- Must be local or willing to relocate
- Expertise in chip design, Verilog and System Verilog
- Knowledge of verification and UVM methodology
- Experience with ATPG tools
- Familiarity with scan insertion tools
- Proficiency in gate-level simulations
- Skills in static timing analysis
- Scripting abilities (Perl/Tcl)
- Familiarity with ATE
- Hands-on expertise with commercial test generation tools for large complex designs
- Strong fundamental knowledge of DFT techniques including JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression
- Experience running test compression software
- Experience using Mentor Tessent or Synopsys DFT Max and Tetramax tools
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