Principal Digital Design Engineer - CXL/PCIe
Description For Principal Digital Design Engineer - CXL/PCIe
Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. We are seeking a Principal Digital Design Engineer-CXL/PCIe with deep expertise in high-performance controller and bridge design, micro-architecture, RTL implementation, and IP integration. The ideal candidate will play a critical role in the development of cutting-edge connectivity solutions.
Key Responsibilities:
- Design and implement high-performance digital solutions, including RTL development and synthesis
- Collaborate with cross-functional teams on IP integration for PCIe/CXL protocols
- Own block-level and full-chip designs from architecture to GDS, focusing on designs at nodes ≤ 16nm
- Ensure timing closure, assess verification completeness, and oversee pre- and post-silicon debug
- Utilize tools from Synopsys/Cadence and apply expertise in UVM-based verification flows
This role offers an opportunity to work on cutting-edge technology in the field of AI and cloud infrastructure connectivity. You'll be part of a team that's transforming modern data-driven applications and contributing to the development of innovative products that are flexible and interoperable.
Join Astera Labs to be at the forefront of connectivity solutions, working with advanced technologies and protocols like PCIe and CXL. This position is ideal for someone who thrives in a collaborative environment, has a strong work ethic, and is passionate about pushing the boundaries of digital design in the semiconductor industry.
Responsibilities For Principal Digital Design Engineer - CXL/PCIe
- Design and implement high-performance digital solutions, including RTL development and synthesis
- Collaborate with cross-functional teams on IP integration for PCIe/CXL protocols
- Own block-level and full-chip designs from architecture to GDS, focusing on designs at nodes ≤ 16nm
- Ensure timing closure, assess verification completeness, and oversee pre- and post-silicon debug
- Utilize tools from Synopsys/Cadence and apply expertise in UVM-based verification flows
Requirements For Principal Digital Design Engineer - CXL/PCIe
- Bachelor's in Electronics/Electrical Engineering (Master's preferred)
- 12+ years of digital design experience, with 5+ years focused on high-speed PCIe/CXL implementation
- Proven expertise in RTL development, synthesis, and timing closure
- Experience with front-end design, gate-level simulations, and design verification
- Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude
- Hands-on experience with high-speed protocols like PCIe/CXL (Gen4+)
- Strong proficiency in System Verilog/Verilog and scripting (Python/Perl)
- Experience with block-level and full-chip design at advanced nodes (≤ 16nm)
- Silicon bring-up and post-silicon debug experience
- Familiarity with Synopsys/Cadence tools and UVM-based design verification
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