Principal Digital Design Engineer-SOC
Description For Principal Digital Design Engineer-SOC
Astera Labs, a leading innovator in connectivity solutions for AI and cloud infrastructure, is seeking a Principal Digital Design Engineer to join their team in Bengaluru, India. This role represents an opportunity to work at the cutting edge of semiconductor design, focusing on high-performance controller and bridge design, micro-architecture, and RTL implementation.
The position requires a seasoned professional with 12+ years of experience in digital design, particularly in processor and full chip implementation. You'll be responsible for designing and implementing high-performance digital solutions, working with advanced nodes (16nm and below), and managing complex system integration tasks. The role combines deep technical expertise in RTL development, synthesis, and timing closure with strategic oversight of block-level and full-chip designs.
Astera Labs' Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions with their COSMOS software suite, delivering scalable and customizable architecture for modern data centers. This role offers the opportunity to work with state-of-the-art technology and contribute to solutions that are transforming modern data-driven applications.
The company values diversity and actively encourages applications from people of all backgrounds, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities. The position offers the chance to work with cutting-edge technology while being part of a company that's making significant impacts in the AI and cloud infrastructure space.
Responsibilities For Principal Digital Design Engineer-SOC
- Design and implement high-performance digital solutions, including RTL development and synthesis
- Collaborate with cross-functional teams on IP integration for processor IPS and peripherals
- Own block-level and full-chip designs from architecture to GDS
- Ensure timing closure, assess verification completeness, and oversee pre- and post-silicon debug
- Utilize tools from Synopsys/Cadence and apply expertise in UVM-based verification flows
Requirements For Principal Digital Design Engineer-SOC
- Bachelor's in Electronics/Electrical engineering (Master's preferred)
- 12+ years of digital design experience, with 4+ years focused on processor, peripherals and full chip implementation
- Proven expertise in RTL development, synthesis, and timing closure
- Experience with front-end design, gate-level simulations, and design verification
- Hands-on experience with processor IP (ARM/ARC)
- Strong proficiency in System Verilog/Verilog and scripting (Python/Perl)
- Experience with block-level and full-chip design at advanced nodes (≤ 16nm)
- Silicon bring-up and post-silicon debug experience
- Familiarity with Synopsys/Cadence tools and UVM-based design verification
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