Senior DFT Engineer
Description For Senior DFT Engineer
Astera Labs is seeking a Senior DFT (Design For Test) Engineer to join their DFT Design team. This role involves developing next-generation connectivity products for leading cloud service providers and server/networking OEMs. The position offers exposure to the full product life-cycle and requires close collaboration with various engineering teams.
Key Responsibilities:
- Develop DFT solutions for complex semiconductor designs
- Work on chip design, verification, and test generation
- Collaborate with multiple engineering teams throughout the product lifecycle
- Implement and optimize test compression techniques
- Conduct gate-level simulations and static timing analysis
Required Qualifications:
- Bachelor's degree in Computer Engineering or Electrical Engineering
- 5+ years of experience as a DFT engineer in a semiconductor company
- Expertise in chip design, Verilog, and System Verilog
- Proficiency in UVM methodology and ATPG tools
- Experience with scan insertion tools and test compression software
- Strong knowledge of DFT techniques (JTAG, ATPG, test pattern translation, yield learning, logic diagnosis)
- Familiarity with ATE and commercial test generation tools
- Scripting skills (Perl/Tcl)
Preferred Experience:
- SOC level verification on large designs
- Working with 93k Tester
- Knowledge of IEEE 1500 Standard or IEEE 1687 standard
- Experience with MBIST and LBIST
Astera Labs values diversity and encourages applications from people of color, LGBTQ+ individuals, veterans, parents, and individuals with disabilities. The company offers a competitive salary based on location and experience.
Join Astera Labs to work on cutting-edge connectivity solutions and be part of a team transforming modern data-driven applications.
Responsibilities For Senior DFT Engineer
- Develop next-generation connectivity products for cloud service providers and server/networking OEMs
- Work on full product life-cycle, from definition to mass production to end of life
- Collaborate closely with all engineering teams, physical design, and other functions
- Implement and optimize DFT solutions for complex semiconductor designs
- Conduct gate-level simulations and static timing analysis
- Perform test pattern generation and optimization
- Contribute to yield learning and logic diagnosis processes
Requirements For Senior DFT Engineer
- Bachelor's degree in Computer Engineering / Electrical Engineering
- 5+ years of experience in a semiconductor company as a DFT engineer
- Expertise in chip design, Verilog and System Verilog
- Proficiency in verification and UVM methodology
- Experience with ATPG tools and scan insertion tools
- Skills in gate-level simulations and static timing analysis
- Scripting abilities (Perl/Tcl)
- Familiarity with ATE
- Hands-on expertise with commercial test generation tools for large complex designs
- Strong fundamental knowledge of DFT techniques (JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression)
- Experience running test compression software
- Experience using Mentor Tessent or Synopsys DFT Max and Tetramax tools
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