Senior Physical Design Engineer
Description For Senior Physical Design Engineer
Astera Labs is seeking a Senior Physical Design Engineer to join their team in Bengaluru, India. The ideal candidate will have a strong background in electrical engineering or computer science, with at least 5 years of experience in complex SoC/silicon product development for Server, Storage, and/or Networking applications.
Key responsibilities include:
- Driving multiple complex designs from architecture to GDSII at both full chip and block levels
- Expertise in synthesis, timing closure, and formal verification
- Working with Cadence and/or Synopsys physical design tools/flows
- Collaborating with IP vendors for both RTL and hard-mac blocks
Required skills and qualifications:
- Bachelor's degree in EE / Computer Science (Master's preferred)
- Hands-on knowledge of synthesis, place and route, timing, extraction, and other backend tools for 16nm or less technologies
- Experience with System Verilog/Verilog
- Familiarity with DFT tools and techniques
- Strong scripting skills in Python or Perl
The ideal candidate will have an entrepreneurial mindset, ability to prioritize tasks, and work with minimal supervision. Experience with DFT test coverage, debug, and ECO methodologies is a plus.
Astera Labs offers a dynamic work environment focused on innovation in AI and cloud infrastructure. Join a team that values diversity and is transforming modern data-driven applications.
Responsibilities For Senior Physical Design Engineer
- Drive multiple complex designs from architecture to GDSII at full chip and block levels
- Perform synthesis, timing closure, and formal verification at block and full-chip levels
- Work with Cadence and/or Synopsys physical design tools/flows
- Collaborate with IP vendors for both RTL and hard-mac blocks
- Contribute to DFT implementation and test coverage
Requirements For Senior Physical Design Engineer
- Bachelor's degree in EE / Computer Science (Master's preferred)
- ≥ 5 years experience in complex SoC/silicon product development
- Expertise in synthesis, timing closure, and formal verification
- Experience with Cadence and/or Synopsys physical design tools/flows
- Knowledge of System Verilog/Verilog
- Experience with DFT tools and techniques
- Strong scripting skills in Python or Perl
- Must be located locally or willing to relocate to Bengaluru, India
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