ASIC DFT Engineer

Broadcom's ASIC Product Division is seeking candidates for a DFT (Design for Testability) position at their Fort Collins, Colorado Development Center. The successful candidate will be responsible for leading DFT programs from chip level DFT specification, through implementation and verification, to successfully releasing products to production.

Key responsibilities include:

• Understanding Broadcom & customer DFT feature requirements & DPPM goals
• Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration
• Working with STA and DI Engineers for design closure for test
• Generating, Verifying & Debugging Test vectors
• Validating & Debugging Test vectors on ATE during silicon bring up
• Assisting with silicon failure analysis, diagnostics & yield improvement
• Interfacing with customers, physical design, and test engineering/manufacturing teams globally
• Innovating newer DFT solutions for 7nm & beyond
• Automating DFT & Test Vector Generation flows

Required skills and experience:

• Strong DFT background (IO and Analog DFT, ATPG, Scan, BIST, etc.)
• Experience with scan insertion and compression tools
• Logic BIST design and debug experience
• ATPG vector generation, simulation, and debugging
• Verilog coding, testbench generation & simulation
• Memory BIST insertion and verification
• Boundary scan verification and test vector generation
• Knowledge of Test-STA and constraints
• Background in IEEE1687, IJTAG, ICL, and PDL
• Excellent problem-solving, debug, root cause analysis, and communication skills

The role requires a Bachelor's degree in Electrical/Electronic/Computer Engineering with 12+ years of relevant industry experience, or a Master's degree with 10+ years of experience.

Broadcom offers competitive compensation, including base salary, annual bonus, equity, and comprehensive benefits package. The company is an equal opportunity employer and values diversity in its workforce.