ASIC DFT Engineer
Description For ASIC DFT Engineer
Broadcom, a global leader in semiconductor and infrastructure software solutions, is seeking an experienced ASIC DFT Engineer for their Fort Collins, Colorado facility. This senior-level position offers a competitive salary range of $107,000 - $171,000 plus comprehensive benefits.
The role focuses on leading DFT programs from chip-level specification through implementation and verification, culminating in successful product releases. The position requires deep expertise in SoC DFT activities within Broadcom's ASIC Products Division, including DFT Architecture, test insertion and verification, pattern generation, and post-silicon debug.
The ideal candidate will have 8+ years of experience with a Bachelor's degree (or 6+ years with a Master's) in Electrical/Electronic/Computer Engineering. Strong technical skills in DFT, including scan insertion, BIST design, ATPG vector generation, and Verilog coding are essential. Programming proficiency in languages like Python, TCL, PERL, or C++ is required.
Key responsibilities include implementing various DFT features, working with global teams, debugging test vectors, and innovating DFT solutions for 7nm technology and beyond. The role offers opportunities to work with cutting-edge technology and interact directly with customers.
Broadcom offers an attractive compensation package including medical, dental, and vision insurance, 401(k) matching, equity participation through ESPP, and various other benefits. The company promotes an inclusive work environment and values diversity in its workforce.
This position is perfect for a seasoned professional looking to make significant contributions to advanced semiconductor testing and validation, while working with a leading technology company that provides opportunities for growth and innovation in the field of ASIC development.
Responsibilities For ASIC DFT Engineer
- Understanding Broadcom & customer DFT feature requirements & DPPM goals & defining DFT specifications for ASIC
- Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration
- Working closely with STA and DI Engineers design closure for test
- Generating, Verifying & Debugging Test vectors before tape release
- Validating & Debugging Test vectors on ATE during silicon bring up phase
- Assisting with silicon failure analysis, diagnostics & yield improvement efforts
- Interfacing with customer, physical design and test teams globally
- Debugging customer returned parts on the ATE
- Innovating newer DFT solutions for 7nm & beyond
- Automating DFT & Test Vector Generation flows
Requirements For ASIC DFT Engineer
- Strong DFT background (IO and Analog DFT, ATPG, Scan, BIST)
- Scan Insertion and scan compression background (DFT Compiler, Mentor TestKompress)
- Logic BIST design and debug experience
- ATPG vector generation, simulation, debug experience (TetraMax, Fastscan)
- Experience in Verilog coding, testbench generation & simulation
- Memory BIST insertion and verification experience (SRAM, CAM, eDRAM)
- Ability to work in multi-disciplined, cross-department environment
- Knowledge in analog and digital circuit design, device physics fundamentals
- Understanding of Si processing, logical and physical synthesis
- Excellent problem solving, debug, root cause analysis and communication skills
- Bachelors in Electrical/Electronic/Computer Engineering with 8+ years experience or Masters with 6+ years experience
- Programming skills in TCL, PERL, RUBY, PYTHON, C++ or similar
Benefits For ASIC DFT Engineer
- Medical, dental and vision plans
- 401(K) participation with company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- Paid holidays
- Paid sick leave
- Vacation time
- Paid Family Leave
- Annual discretionary bonus
- Equity compensation
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