ASIC Digital Design Verification Engineer
Description For ASIC Digital Design Verification Engineer
Broadcom, a global technology leader in semiconductor and infrastructure software solutions, is seeking a Staff-level ASIC Digital Design Verification Engineer for their San Jose office. This role offers a competitive salary range of $119,000 - $190,000 with comprehensive benefits including medical coverage and equity compensation.
The position requires a seasoned professional with 8+ years of experience (or 6+ with MS degree) in ASIC Design Verification. The ideal candidate will possess deep expertise in System Verilog, UVM, and verification coverage matrix, along with strong experience in developing checkers, scoreboards, and writing assertions. Knowledge of ARM core architecture, various bus protocols, and embedded systems programming is essential.
This role presents an opportunity to work with cutting-edge technology in semiconductor design, utilizing industry-standard EDA tools from Synopsys/Cadence. The position demands both technical excellence and strong communication skills, as you'll be collaborating with various technical and management levels.
Broadcom offers a comprehensive benefits package including medical, dental, and vision coverage, 401(k) matching, stock purchase programs, and various leave benefits. The company promotes an inclusive work environment and values diversity in its workforce. This role is perfect for someone looking to advance their career in semiconductor design verification while working for a global technology leader.
Requirements For ASIC Digital Design Verification Engineer
- BSc in Electrical Engineering or Computer Engineering with 8+ years of experience or MS with 6+ years of experience
- Deep knowledge of System Verilog, UVM and verification coverage matrix
- Experience in developing checker, scoreboard & writing assertions
- Knowledge of ARM core, APB/AHB bus protocol, Serial peripherals
- Experience with randomized vectors for analog and digital behavioral model verification
- Knowledge of Synopsys/Cadence EDA tools
- Working knowledge of Assembly, C, and C++ languages
- Experience with GLS, zero delay & non-zero delay parasitic annotated simulations
- Strong written and verbal communication skills
- Excellent time and task management skills
Benefits For ASIC Digital Design Verification Engineer
- Medical, dental and vision plans
- 401(K) with company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- Paid holidays
- Paid sick leave
- Vacation time
- Paid Family Leave
- Annual bonus
- Equity compensation
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