ASIC Physical Design Engineer

A global technology leader that designs, develops and supplies semiconductor and infrastructure software solutions
Embedded
Senior Software Engineer
In-Person
5+ years of experience
Enterprise SaaS

Description For ASIC Physical Design Engineer

Broadcom, a global technology leader in semiconductor and infrastructure software solutions, is seeking an experienced ASIC Physical Design Engineer for their Singapore-Yishun location. This role focuses on advanced semiconductor design using cutting-edge process technologies from 7nm down to 2nm. The position requires expertise in working with commercial and in-house EDA tools from industry leaders like Synopsys, Cadence, and Siemens.

The ideal candidate will be responsible for implementing complex digital blocks with up to 12Mgates/3M instances, managing the entire design flow from RTL synthesis to GDS. This includes crucial stages such as placement, clock tree synthesis, detailed routing, and various verification processes. The role demands strong multitasking abilities to handle multiple block assignments simultaneously.

The position offers an opportunity to work at the forefront of semiconductor technology, contributing to projects that involve hundreds of millions of gates in advanced process nodes. Candidates should possess strong technical foundations in electrical, electronics, or computer engineering, complemented by significant industry experience.

Broadcom maintains a strong commitment to equal opportunity employment and values diversity in its workforce. The company offers a collaborative environment where professionals can contribute to cutting-edge technology development while working alongside industry experts. This role represents an excellent opportunity for experienced engineers looking to advance their careers in semiconductor design at a global technology leader.

Last updated 22 days ago

Responsibilities For ASIC Physical Design Engineer

  • Utilize commercial and in-house EDA tools for design and implementation of 100 ~ 400 million gate integrated circuits in 7nm/5nm/3nm/2nm process technologies
  • Proficient with a full Netlist/Gates to GDS flow, inclusive of all construction stages for complex digital blocks of up to 12Mgates/3M instances with embedded macros
  • Handle multiple block assignments in parallel

Requirements For ASIC Physical Design Engineer

  • Degree, Masters or PhD in Electrical/Electronics/Computer engineering
  • Minimum of 5 years or more experience in a relevant field
  • Proficiency in UNIX/Linux and scripting languages is advantageous

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