ASIC Physical Design Engineer

A global technology leader that designs, develops and supplies semiconductor and infrastructure software solutions.
Singapore
Embedded
Senior Software Engineer
In-Person
5+ years of experience
Enterprise SaaS

Description For ASIC Physical Design Engineer

Broadcom, a global leader in semiconductor and software solutions, is seeking a Senior ASIC Physical Design Engineer to join their team in Singapore. This role focuses on designing and implementing complex integrated circuits using cutting-edge process technologies from 7nm down to 2nm. The position requires expertise in working with commercial and in-house EDA tools from industry leaders like Synopsys, Cadence, and Siemens.

The ideal candidate will be responsible for managing the complete Netlist/Gates to GDS flow, handling complex digital blocks with embedded macros, and working on multiple assignments simultaneously. This role offers the opportunity to work at the forefront of semiconductor technology, contributing to Broadcom's innovative solutions that power various industries.

As an ASIC Physical Design Engineer, you'll be part of a team that pushes the boundaries of semiconductor design, working with state-of-the-art tools and technologies. The position requires strong technical skills in UNIX/Linux environments and scripting languages, combined with a solid educational background in electrical, electronics, or computer engineering.

Broadcom offers a diverse and inclusive work environment, considering qualified applicants regardless of their background. The company's global presence and commitment to technological advancement make it an ideal place for professionals looking to make a significant impact in the semiconductor industry. Join Broadcom to be part of a team that's shaping the future of technology through innovative semiconductor and software solutions.

Last updated 4 minutes ago

Responsibilities For ASIC Physical Design Engineer

  • Utilize commercial and in-house EDA tools for design and implementation of 100 ~ 400 million gate integrated circuits in 7nm/5nm/3nm/2nm process technologies
  • Handle full Netlist/Gates to GDS flow, including RTL synthesis, placement, clock tree synthesis, detailed routing, physical verification, formal verification and timing analysis
  • Manage complex digital blocks of up to 12Mgates/3M instances with embedded macros
  • Handle multiple block assignments in parallel

Requirements For ASIC Physical Design Engineer

Linux
  • Degree, Masters or PhD in Electrical/Electronics/Computer engineering
  • Minimum of 5 years or more experience in a relevant field
  • Proficiency in UNIX/Linux and scripting languages

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